NDLI: Organizing committee

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2015 International Conference on Field Programmable Technology (FPT)

2013 International Conference on Field-Programmable Technology (FPT)

2012 International Conference on Field-Programmable Technology

2011 International Conference on Field-Programmable Technology

2010 International Conference on Field-Programmable Technology

2009 International Conference on Field-Programmable Technology

Message from the general chair and program co-chairs

Organizing committee

Packets everywhere: The great opportunity for field programmable technology

From dynamic reconfiguration to self-reconfiguration: Invasive algorithms and architectures

ASKAP beamformer

Design of a Vehicle-to-Vehicle communication system on reconfigurable hardware

Implementation of a foveal vision mapping

An architecture of optimised SIFT feature detection for an FPGA implementation of an image matcher

Exploiting memory customization in FPGA for 3D stencil computations

Towards a balanced ternary FPGA

Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design

Simulation of a QCA-based CLB and a multi-CLB application

A flexible DSP block to enhance FPGA arithmetic performance

VMATCH: Using logical variation to counteract physical variation in bottom-up, nanoscale systems

PGR: Period and glitch reduction via clock skew scheduling, delay padding and GlitchLess

A detailed delay path model for FPGAs

Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells

ASIF: Application Specific Inflexible FPGA

The challenges of using an embedded MPI for hardware-based processing nodes

Transforming write collisions in block RAMs into security applications

FPGA implementation of an invasive computing architecture

FFPU: Fractured floating point unit for FPGA soft processors

Rapid synthesis and simulation of computational circuits in an MPPA

Self-hosted placement for massively parallel processor arrays

Congestion-driven regional re-clustering for low-cost FPGAs

An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning

Differential Power Analysis resistance of Camellia and countermeasure strategy on FPGAs

Parallelizing sparse Matrix Solve for SPICE circuit simulation using FPGAs

K-loops: Loop skewing for Reconfigurable Architectures

Profile driven data-dependency analysis for improved high level language hardware synthesis

Automatic optimisation of MapReduce designs by geometric programming

Scheduling and 2D placement heuristics for partially reconfigurable systems

FPGA vs. MPPA for Positron Emission Tomography pulse processing

Efficient implementation of fast redundant number adders for long word-lengths in FPGAs

A parallel spiking neural network simulator

FPGA vs. GPU for sparse matrix vector multiply

American option pricing on reconfigurable hardware using Least-Squares Monte Carlo method

A high performance FPGA-based core for phylogenetic analysis with Maximum Parsimony method

Area, delay, power, and cost trends for metal-programmable structured ASICs (MPSAs)

An architecture for exploiting coarse-grain parallelism on FPGAs

Automatic instrumentation of profilers for FPGA-based design space exploration

A novel fast online placement algorithm on 2D partially reconfigurable devices

Exploring the evolution of NoC-based Spiking Neural Networks on FPGAs

Methodology for designing statically scheduled application-specific SDRAM controllers using constrained local search

An ASIC implementation of phase correlation based on run-time reconfiguration technique

Throughput optimization by pipeline alignment of a Self Synchronous FPGA

Real-time detection of rotated patterns using FPGA

Targeted configurable caches

An energy and power consumption analysis of FPGA routing architectures

Novel hardening techniques against differential power analysis for multiplication in $GF(2^{n})$

A module-based partial reconfiguration design for solving sparse linear systems over GF(2)

High speed merged-datapath design for run-time reconfigurable systems

Using FPGA resources for direct generation of multivariate Gaussian random numbers

Efficient hardware generation for Dynamic Programming problems

SPY vs. SLY: Run-time thread-scheduler aware reconfigurable hardware allocators

ICAP-I: A reusable interface for the internal reconfiguration of Xilinx FPGAs

Dynamic reconfiguration in a PSoC device

Low power image processing using MuCCRA-3: A Dynamically Reconfigurable Processor Array

Using a reconfigurable compute cluster for the acceleration of neural networks

FPGA-in-the-loop-simulations for dynamically reconfigurable applications

FloRA: Coarse-grained reconfigurable architecture with floating-point operation capability

Demonstration of hardware-accelerated formal verification

Demonstration of the fault recognition and recovery of FPGA circuits by means of Cytokine-Formal Immune Networks

Performance comparison of GPU and FPGA architectures for the SVM training problem

A distributed operating system supporting strong mobility of reconfigurable computing applications in a swarm of unpiloted airborne vehicles

Optimization of modular multiplication on FPGA using don't care conditions

Round-based priority arbitration for predictable and reconfigurable Network-on-Chip

Reducing dynamic power consumption in FPGAs using precomputation

Automated application acceleration using software to hardware transformation

A study on interconnection networks of the Dynamically Reconfigurable Processor Array MuCCRA

Routing optimization for hybrid FPGAs

Benchmark results for asynchronous high-speed FPGAs focusing on high performance digital signal processing

Option pricing with multi-dimensional quadrature architectures

Configurable CMOS H-tree logic module

DRAFT: Flexible interconnection network for dynamically reconfigurable architectures

Reconfigurable acceleration of neural models with gap junctions

Modelling degradation in FPGA lookup tables

FPGA implementation of mixed integer quadratic programming solver for mobile robot control

A flexible FPGA-based MIMO geometric fading channel simulator for rapid prototyping

Automated dynamic reconfiguration for high-performance regular expression searching

rSesame - A generic system-level runtime simulation framework for reconfigurable architectures

Flexible framework for commodity FPGA cluster computing

Efficient reconfigurable architectures for 3D medical image compression

Automatic system architecture synthesis for FPGA-based reconfigurable computers

Operating system management of reconfigurable hardware computing systems

The effect of node size, heterogeneity, and network size on FPGA based NoCs

Reconfigurable sparse/dense matrix-vector multiplier

QoS-aware dynamic power management for coarse-grained reconfigurable architecture

A floating-point accumulator for FPGA-based high performance computing applications

A high-performance double precision accumulator

3-tier reconfiguration model For FPGAs using Hardwired Network on Chip

HW/SW co-design of Identity-Based Encryption using a custom instruction set

Run time mapping of adaptive applications onto homogeneous NoC-based reconfigurable architectures

FPGA implementation of a 64-Bit BID-based decimal floating-point adder/subtractor

An FPGA-based Sudoku Solver based on Simulated Annealing methods

The TU Delft sudoku solver on FPGA

An initial specific processor for Sudoku solving

Hub Page - The 2009 International Conference on Field-Programmable Technology

2008 International Conference on Field-Programmable Technology

2007 International Conference on Field-Programmable Technology

2006 IEEE International Conference on Field Programmable Technology

Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005.

Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)

Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798)

2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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