NDLI: HW/SW interface synthesis based on Avalon bus specification for Nios-oriented SoC design

Content Provider	IEEE Xplore Digital Library
Author	Feng Lin Haili Wang Jinian Bian
Copyright Year	2005
Description	Author affiliation: Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China (Feng Lin; Haili Wang; Jinian Bian)
Abstract	HW/SW interface synthesis plays an important role in systems-on-chip design. In this paper, we propose a new HW/SW interface synthesis design method aiming at the Nios-based SoC platform. Our main motivation is to separate the consideration of interface circuits from HW/SW modules design, leaving SW modules in the Nios processor and HW modules in the FPGA as peripherals. Different interface circuits will be kept as templates in interface library customized for different bus structures and transfer modes. When interface synthesizing, HW modules themselves are left with no changes; they only need to select different interface templates from the library according to the structure and transfer mode of the bus they connect to. The experimental results show this design methodology can efficiently solve the HW/SW interface synthesis problems on the Nios platform mentioned above well.
Starting Page	305
Ending Page	306
File Size	236125
Page Count	2
File Format	PDF
ISBN	0780394070
DOI	10.1109/FPT.2005.1568573
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-12-11
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit synthesis Design methodology Libraries Registers Driver circuits Computer science Field programmable gate arrays Hardware design languages Integrated circuit synthesis Protocols
Content Type	Text
Resource Type	Article

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