NDLI: gNBX - reconfigurable hardware acceleration of self-organizing maps

Content Provider	IEEE Xplore Digital Library
Author	Pohl, C. Franzmeier, M. Porrmann, M. Ruckert, U.
Copyright Year	2004
Description	Author affiliation: Heinz Nixdorf Inst., Paderborn Univ., Germany (Pohl, C.; Franzmeier, M.; Porrmann, M.; Ruckert, U.)
Abstract	In this work a new FPGA based hardware accelerator (gNBX) for self-organizing maps is introduced. New principles for hardware acceleration of self-organizing maps, which increase the degree of parallelity and therefore the acceleration gain was presented. Our technology independent design description can be mapped on application specific integrated circuits if very high performance is required, as well as on field programmable gate arrays (FPGAs), which offer mid level performance (a speed up factor of up to 70 in comparison with PCs for typical datasets is achieved) at relatively low costs. Additionally, FPGAs offer the flexibility to adapt the hardware to the changing requirements of the application during runtime. Therefore, the hardware can be exploited optimally at all times during the simulation process. Several benchmark scenarios with well known datasets shows the performance of our system.
Starting Page	97
Ending Page	104
File Size	558678
Page Count	8
File Format	PDF
ISBN	0780386515
DOI	10.1109/FPT.2004.1393256
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-12-06
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Acceleration Self organizing feature maps Field programmable gate arrays Neurons Personal communication networks Costs Data analysis Circuit simulation Fabrication
Content Type	Text
Resource Type	Article

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