NDLI: Scalable 10Gbps TCP/IP Stack Architecture for Reconfigurable Hardware

Content Provider	IEEE Xplore Digital Library
Author	Sidler, D. Alonso, G. Blott, M. Karras, K. Vissers, K. Carley, R.
Copyright Year	2015
Description	Author affiliation: Dept. of Comput. Sci., ETH Zurich, Zurich, Switzerland (Sidler, D.; Alonso, G.) \|\| Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA (Carley, R.) \|\| Xilinx Res., Dublin, Ireland (Blott, M.; Karras, K.; Vissers, K.)
Abstract	TCP/IP is the predominant communication protocol in modern networks but also one of the most demanding. Consequently, TCP/IP offload is becoming increasingly popular with standard network interface cards. TCP/IP Offload Engines have also emerged for FPGAs, and are being offered by vendors such as Intilop, Fraunhofer HHI, PLDA and Dini Group. With the target application being high-frequency trading, these implementations focus on low latency and support a limited session count. However, many more applications beyond high-frequency trading can potentially be accelerated inside an FPGA once TCP with high session count is available inside the fabric. This way, a network-attached FPGA on ingress and egress to a CPU can accelerate functions such as encryption, compression, memcached and many others in addition to running the complete network stack. This paper introduces a novel architecture for a 10Gbps line-rate TCP/IP stack for FPGAs that can scale with the number of sessions and thereby addresses these new applications. We prototyped the design on a VC709 development board, demonstrating compatibility with existing network infrastructure, operating at full 10Gbps throughput full-duplex while supporting 10,000 sessions. Finally, the design has been described primarily using high-level synthesis, which accelerates development time and improves maintainability.
Starting Page	36
Ending Page	43
File Size	191419
Page Count	8
File Format	PDF
ISBN	9781479999699
DOI	10.1109/FCCM.2015.12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-02
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	IP networks Engines Protocols Data structures Ports (Computers) Field programmable gate arrays High-level Synthesis (HLS) TCP/IP Reconfigurable Hardware 10G network stack High session count
Content Type	Text
Resource Type	Article

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