NDLI: GraphStep: A System Architecture for Sparse-Graph Algorithms

Content Provider	IEEE Xplore Digital Library
Author	deLorimier, M. Kapre, N. Mehta, N. Rizzo, D. Eslick, I. Rubin, R. Uribe, T.E. Knight, T.F. DeHon, A.
Copyright Year	2006
Description	Author affiliation: Dept. of Comput. Sci., California Inst. of Technol., Pasadena, CA (deLorimier, M.; Kapre, N.; Mehta, N.; Rizzo, D.; Eslick, I.; Rubin, R.; Uribe, T.E.; Knight, T.F.; DeHon, A.)
Abstract	Many important applications are organized around long-lived, irregular sparse graphs (e.g., data and knowledge bases, CAD optimization, numerical problems, simulations). The graph structures are large, and the applications need regular access to a large, data-dependent portion of the graph for each operation (e.g., the algorithm may need to walk the graph, visiting all nodes, or propagate changes through many nodes in the graph). On conventional microprocessors, the graph structures exceed on-chip cache capacities, making main-memory bandwidth and latency the key performance limiters. To avoid this "memory wall," we introduce a concurrent system architecture for sparse graph algorithms that places graph nodes in small distributed memories paired with specialized graph processing nodes interconnected by a lightweight network. This gives us a scalable way to map these applications so that they can exploit the high-bandwidth and low-latency capabilities of embedded memories (e.g., FPGA Block RAMs). On typical spreading-activation queries on the ConceptNet Knowledge Base, a sample application, this translates into an order of magnitude speedup per FPGA compared to a state-of-the-art Pentium processor
Starting Page	143
Ending Page	151
File Size	179312
Page Count	9
File Format	PDF
ISBN	0769526616
DOI	10.1109/FCCM.2006.45
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-04-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Bandwidth Random access memory Computer architecture Hardware SDRAM Microprocessors Aggregates Numerical simulation Delay
Content Type	Text
Resource Type	Article

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