NDLI: A pipelined SoPC architecture for 2.5 Gbps network processing

Content Provider	IEEE Xplore Digital Library
Author	Toal, C. Sezer, S. Xing Yu
Copyright Year	2003
Description	Author affiliation: Sch. of Electr. & Electron. Eng., Queen's Univ., Belfast, UK (Toal, C.; Sezer, S.; Xing Yu)
Abstract	This paper presents the architecture and implementation of a 2.5 Gbps Programmable Point-to-Point-Protocol Processor (P5) on a Virtex II FPGA (field programmable gate array). A 32-bit wide pipelined processor circuit is implemented for layer 2 frame processing and a Leon processor core is embedded for higher layer PPP (point-to-point protocol) control protocol processing. An AMBA bus interface is used to interlink the Leon processor to the hardware frame processing unit and presents a standard interface allowing easy retargeting to other processor platforms. Complex memory control is implemented to enable the microprocessor to handle the extreme data rate. The high-level system breakdown is described and Virtex II synthesis results are presented.
Sponsorship	IEEE Comput. Soc. Tech. Committee on Comput. Archit
Starting Page	271
Ending Page	272
File Size	213128
Page Count	2
File Format	PDF
ISBN	0769519792
DOI	10.1109/FPGA.2003.1227266
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-04-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Protocols Computer architecture Physical layer Hardware Microprocessors Field programmable gate arrays Communication system control Bandwidth Quality of service Payloads
Content Type	Text
Resource Type	Article

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