NDLI: A super-serial Galois fields multiplier for FPGAs and its application to public-key algorithms

Content Provider	IEEE Xplore Digital Library
Author	Orlando, G. Paar, C.
Copyright Year	1999
Description	Author affiliation: GTE Gov. Syst. Corp., Needham Heights, MA, USA (Orlando, G.)
Abstract	This contribution introduces a scalable multiplier architecture for Galois field GF(2/sup k/) amenable for field programmable gate arrays (FPGAs) implementations. This architecture is well suited for the implementation of public-key cryptosystems which require programmable multipliers in large Galois fields. The architecture trades a reduction in resources with an increase in the number of clock cycles. This architecture is also fine grain scalable in both the time and the area (or logic) dimensions thus facilitating implementations that maximize their use of finite FPGA resources while achieving fast computational speed. This leads to an architecture that requires less resources than traditional bit serial multipliers, which we demonstrated with implementations of multipliers in the field GF(2/sup 167/). Our results demonstrate that for this field one can realize super-serial multipliers that use 2.76 times fewer function generators and 6.84 times fewer flip-flops than their serial multiplier counterparts. We also extrapolated the performance of these multipliers in an elliptic curve cryptosystem.
Starting Page	232
Ending Page	239
File Size	237178
Page Count	8
File Format	PDF
ISBN	0769503756
DOI	10.1109/FPGA.1999.803685
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-04-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Galois fields Field programmable gate arrays Public key Computer architecture Logic Elliptic curve cryptography Arithmetic Polynomials Public key cryptography Clocks
Content Type	Text
Resource Type	Article

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