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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Bolzani, L. Sanchez, E. Schillaci, M. Squillero, G. |
| Copyright Year | 2007 |
| Description | Author affiliation: Politecnico di Torino, Turin (Bolzani, L.; Sanchez, E.; Schillaci, M.; Squillero, G.) |
| Abstract | Research community has not investigated as deeply as necessary the test generation problem of peripheral modules inside a system-on-a-chip (SoC), yet. Testing process for a peripheral core requires two distinct but highly correlated tasks: peripheral configuration and peripheral exercising. The configuration task is usually performed by an assembly program executed by the microprocessor within the SoC; whereas peripheral exercising directly concerns to the use of the device, which may be activated by both the executed program and a carefully devised set of external stimuli. When embedded in a SoC, peripheral cores introduce new issues for their testing. In this paper an automatic approach able to co- evolve assembly programs and stimuli sets for peripheral cores embedded in a SoC is described. The presented approach is based on an evolutionary algorithm that exploits high-level simulation and gathers coverage metrics information to produce the test sets. The proposed method considerably reduces the required efforts to produce a suitable test set with respect to the previous approaches, broadening its applicability and increasing its usefulness. |
| Starting Page | 3474 |
| Ending Page | 3481 |
| File Size | 357849 |
| Page Count | 8 |
| File Format | |
| ISBN | 9781424413393 |
| DOI | 10.1109/CEC.2007.4424922 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-09-25 |
| Publisher Place | Singapore |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Testing Evolutionary computation Linear discriminant analysis |
| Content Type | Text |
| Resource Type | Article |
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