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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chari, K.S. Sharma, M. |
| Copyright Year | 2013 |
| Description | Author affiliation: IC Layout Design Registry, New Delhi, India (Sharma, M.) || Gov. of India, New Delhi, India (Chari, K.S.) |
| Abstract | Integrated Circuits (IC) have evolved over the last few decades from modest circuit complexities to highly complex circuit realizations in meeting the market needs. Considering the heavy investments of time, manpower and financial resources in the development of the advanced chips, the original developers of the chip, per force, take steps to protect the various Intellectual Properties (IP) through appropriate IP regimes operating in their countries. In the competitive world of numerous product ranges and less time to market the products, the probabilities of infringements i.e copying of earlier works into the circuits is increasing and hence, there is severe need of capturing the circuit elements with infringements. The IP registering authorities would assess and in some cases evaluate the IC Layout Design filings made for the chip submitted for IP registration including absence of infringements. A well informed developer will also be vigilant to monitor the market to trace any illegal circuit infringement business through copying of their chip works. From these perspectives, it can be seen that screening of the IC Layout Designs (ICLDs) in detail including comparing them with suspicious candidates becomes vital. |
| Sponsorship | IEEE |
| Starting Page | 1305 |
| Ending Page | 1308 |
| File Size | 175835 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781467357593 |
| e-ISBN | 9781467357586 |
| DOI | 10.1109/CICT.2013.6558303 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-04-11 |
| Publisher Place | South Korea |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Integrated circuits Geometry Guidelines and Infrastructure for Layout comparison Visualization Databases Layout Intellectual Property Data mining IP networks ICLD comparison and validation techniques IC Layouts |
| Content Type | Text |
| Resource Type | Article |
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