NDLI: Single phase 9 level MLDCL inverter with half bridge cell topology: Performance analysis

Content Provider	IEEE Xplore Digital Library
Author	Belekar, R.A. Nakade, R.P. Chahande, N.M. Parchandekar, S.K.
Copyright Year	2013
Description	Author affiliation: Electron. Dept., Walchand Coll. of Eng., Sangli, India (Belekar, R.A.; Nakade, R.P.; Chahande, N.M.; Parchandekar, S.K.)
Abstract	This paper presents the implementation of Single Phase 9 level MLDCL Inverter with Half Bridge Cell topology. For N level inverter, (N-1)/2 half bridge cells are required with the same number of voltage sources. One voltage source is used for each half bridge cell. These N levels are obtained in every half cycle of the output. So, in all 2×N levels are obtained in each full cycle. In the proposed inverter topology, 4 Half Bridge Cells are used along with 4 voltage sources, each of 24V DC. These half bridges are connected in series to form a Multilevel DC Link (MLDCL). The DC link provides 9 levels in each half cycle. The output obtained from this link is of unidirectional nature. H-Bridge network is connected through Multilevel DC Link and used to convert unidirectional output into bidirectional output. Power MOSFETs are used as switching devices. Each half bridge cell uses two MOSFETs whereas H-Bridge requires four MOSFETs. In this inverter topology, twelve Power MOSFETs along with gate drive circuit for each MOSFET is used. The simulation and experimental results are included to verify the working principle of Single Phase 9 level MLDCL Inverter with Half Bridge Cell topology and the Total Harmonic Distortion (THD) in each case is measured.
Starting Page	681
Ending Page	685
File Size	483884
Page Count	5
File Format	PDF
ISBN	9781467360272
e-ISBN	9781467360302
DOI	10.1109/ICPEC.2013.6527743
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-02-06
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Cascaded Multilevel Inverter MOSFET Total Harmonic distortion (THD) H Bridge Cascaded Half Bridge Cells Bridge circuits Switches Logic gates Inverters Topology Voltage control Multilevel DC Link
Content Type	Text
Resource Type	Article

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