NDLI: A low power implementation of PSK modems in FPGA with reconfigurable filter and digital NCO using PR for SDR and CR applications

Content Provider	IEEE Xplore Digital Library
Author	Arun Kumar, K.A.
Copyright Year	2012
Description	Author affiliation: Centre for Development of Advanced Computing, Trivandrum, India (Arun Kumar, K.A.)
Abstract	The role of FPGAs in software defined Radios (SDR) and Cognitive radios (CR) are very significant. These radios have to load different waveform depending on their requirements which may use different source coding, channel coding and modulation schemes. The user has to load large bit files even for small changes in the waveforms. In SDRs and CRs the configuration time and power consumption plays significant role: for example, a virtex-7 FPGA takes 500ms to complete configuration. If the waveforms design is made Partially Reconfigurable then the configuration time and the Hardware usage can be saved. The Objective of this work is to make the Modulation and demodulation (PSK) Schemes partially reconfigurable. The paper describes the Design and Implementation of Phase Shift keying (PSK) Modulation and demodulation in FPGA using Partial Re-configuration (PR). This work involves the Design and implementation of BPSK, QPSK, 8-PSK and 16-PSK modulation and demodulation schemes in FPGA. There is a RRC Filter and a Digital Up converter followed by the modulators and there is a Digital Down converter in the demodulator section. The user can swap between different modulation and demodulation schemes during runtime by configuring a control register in FPGA. The Implementation of these PSKs shares a common hardware, which is the Static Part and there is a Dynamic part too. In the PR, the user has to load the bit stream for the Dynamic part only, and not the entire bit stream. This will be smaller in size compared to the large bit file. The Up/Down converter design consists of two DDS modules and the demodulator part consists of a four DDS modules, which forms the static part of the design. By designing the entire waveform using partial Reconfiguration, the waveform can be made as part of the Platform realized. Here using Partial reconfiguration the Distributed Arithmetic (DA) architecture the power consumption is very much reduced.
Starting Page	192
Ending Page	197
File Size	2892361
Page Count	6
File Format	PDF
ISBN	9781467326353
e-ISBN	9781467326360
DOI	10.1109/ICGT.2012.6477971
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-12-18
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	SDR FPGA SoC Switches Generators RTL Partial Reconfiguration CR Phase shift keying DDS Mathematical model Field programmable gate arrays Demodulation
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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