NDLI: A heterogeneous system architecture for low-power wireless sensor nodes in compute-intensive distributed applications

Content Provider	IEEE Xplore Digital Library
Author	Engel, A. Koch, A. Siebel, T.
Copyright Year	2015
Description	Author affiliation: Res. Div. Smart Struct., Fraunhofer LBF, Darmstadt, Germany (Siebel, T.) \|\| Embedded Syst. & Applic. Group, Tech. Univ. Darmstadt, Darmstadt, Germany (Engel, A.; Koch, A.)
Abstract	Wireless Sensor Networks (WSNs) are a key technology for future social and industrial developments. With increasingly complex applications, the compute demands for in-node / in-network processing have been growing steadily, while the capabilities of energy-harvesting or -storage systems have advanced only slowly. We present the Hardware-Accelerated Low Power Mote (HaLoMote), a heterogeneous system architecture for a wireless sensor node that achieves significantly better energy efficiency than traditional approaches, even for demanding applications requiring sensor sample rates of hundreds of Hertz. The paper discusses an evolution of the node hardware architecture and details the implementation of a signal processing chain required for Structural Health Monitoring (SHM) applications. The measurement accuracy of the WSN-based data acquisition system is compared against a wire-bound laboratory system showing that the dominant eigenfrequencies of a monitored structure can be detected with less than 1% error. Furthermore, the runtime and power requirements of the HaLoMote are compared against various software processors typically used for conventional WSN architectures. It can be shown that the HaLoMote is 2.3 times more energy-efficient than a state-of-the-art ARM Cortex-M3 based device.
Starting Page	636
Ending Page	644
File Size	1541010
Page Count	9
File Format	PDF
e-ISBN	9781467367738
DOI	10.1109/LCNW.2015.7365908
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-10-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wireless communication Wireless sensor networks Nonvolatile memory Ferroelectric films Random access memory Computer architecture Field programmable gate arrays
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in