NDLI: Exploring the speed limit of SM2

Content Provider	IEEE Xplore Digital Library
Author	Zhenwei Zhao Guoqiang Bai
Copyright Year	2014
Description	Author affiliation: Inst. of Microelectron., Tsinghua Univ., Beijing, China (Guoqiang Bai) \|\| Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China (Zhenwei Zhao)
Abstract	In this paper, we explore the serial and parallel point multiplication speed limit of SM2 public key cryptographic algorithm. The optimization criteria for our design is speed, we carry out a thorough analysis on SM2 point multiplication structure and summarize three main factors that contributes to the ultra high-speed realization of point multiplication: the performance of modular multiplier, point coordinates representation and scheduling, scalar representation. For the first time, we introduce a one-cycle 256-bit multiplier to speedup point multiplication. Based on the multiplier, we rearrange the scheduling algorithm of point doubling and addition. A detailed performance comparison between NAF and w-NAF encoding is also conducted. Synthesized in 0.13μm CMOS standard cell library, our serial architecture can perform more than 49000 point multiplications per second, the fastest in the open literature. With 2 multipliers in parallel, the speed can reach as high as 56617. However, the multiplier utilization in parallel architecture is only 66.7%, so we propose to use multi-cores instead of multi-multipliers scheme to obtain better area-time product.
Starting Page	456
Ending Page	460
File Size	645030
Page Count	5
File Format	PDF
ISBN	9781479947201
e-ISBN	9781479947195
DOI	10.1109/CCIS.2014.7175778
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-11-27
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Program processors High Speed Scheduling algorithms ECC Point Multiplication Elliptic curve cryptography SM2 Hardware Parallel architectures Parallel
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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