NDLI: FACE: Fast and Customizable Sorting Accelerator for Heterogeneous Many-core Systems

Content Provider	IEEE Xplore Digital Library
Author	Kobayashi, R. Kise, K.
Copyright Year	2015
Description	Author affiliation: Tokyo Inst. of Technol., Tokyo, Japan (Kobayashi, R.; Kise, K.)
Abstract	Performance improvements of a single-core processor relying on high clock rates reached the limit. Instead of a single-core processor, multi-core and many-core processors have been mainstream to accelerate applications by parallel processing. Year by year, the number of cores integrated in a single chip has been increased due to improvements of semiconductor integration technologies depending on Moore's Law. On the other hand, Moore's Law will be ended in the near future. This means that the approaches relying on the increase in the number of cores will be hopeless, thus we have to consider other effective ways. One of them is to design application specific hardware. Several research organizations have explored it and reported its remarkable findings. We focus on such an acceleration approach with dedicated hardware. As a case study with dedicated hardware, we present a sorting acceleration method. Sorting is an extremely important computation kernel that should be accelerated in a lot of fields, such as databases, image processing, data compression, etc. We propose a sorting accelerator combining Sorting Network and Merge Sorter Tree, and detail the design and implementation. Our proposed sorting accelerator is customizable, thus designers can implement a sorting accelerator composed of required hardware resources by means of tuning design parameters. Our experiments show that the proposed hardware achieves up to 10.06x sorting performance, compared with Intel Core i7-4770 operating at 3.4GHz, when sorting 256M 32-bits integer elements. In order to allow every designer to easily and freely use this accelerator, the RTL source code is released as an open-source hardware.
Starting Page	49
Ending Page	56
File Size	664617
Page Count	8
File Format	PDF
e-ISBN	9781479986705
DOI	10.1109/MCSoC.2015.40
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-09-23
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Customizable Radiation detectors Random access memory Shift registers Hardware Acceleration Open source Hardware specialization Fast Field programmable gate arrays Sorting
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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