NDLI: An Efficient Implementation of the Hough Transform Using DSP Slices and Block RAMs on the FPGA

Content Provider	IEEE Xplore Digital Library
Author	Xin Zhou Ito, Y. Nakano, K.
Copyright Year	2013
Description	Author affiliation: Dept. of Inf. Eng., Hiroshima Univ., Higashi-Hiroshima, Japan (Xin Zhou; Ito, Y.; Nakano, K.)
Abstract	Since FPGA chips maintain relatively low price and its programmable features, it is widely used in those fields which need to update architecture or functions frequently such as communication and education areas. Especially, in mobile devices that recently require the ability to perform computation such as real-time image processing, FPGAs are promising devices. Recent FPGAs have hundreds of embedded DSP slices and block RAMs. For example, Xilinx Virtex-6 Family FPGAs have a DSP48E1 slice, which is a configurable logic block equipped with fast multipliers, adders, pipeline registers, and so on. They also have a dual-port memory with 18Kbits as a block RAM. Therefore, one of the most important key techniques for accelerating computation using such FPGAs is an efficient usage of DSP slices and block RAMs. The main contribution of this paper is to present a new FPGA architecture for the Hough transform for all the pixel data input in raster scan order. The architecture uses 90 DSP48E1 slices and 181 block RAMs with 18Kbits that work in parallel. The experimental results show that this implementation runs in 247.525MHz and given a binary image of size n × n, our circuit can perform in $n^{2}$ + √(2)n + 379 clock cycles.
Starting Page	85
Ending Page	90
File Size	583925
Page Count	6
File Format	PDF
ISBN	9780769550862
DOI	10.1109/MCSoC.2013.29
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-09-26
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Line detection Image processing FPGA Random access memory Transforms Registers Hough transform Embedded DSP slices Digital signal processing Computer architecture Embedded block RAMs Field programmable gate arrays Clocks
Content Type	Text
Resource Type	Article

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