NDLI: Enclosing the modeling error in analog behavioral models using neural networks and affine arithmetic

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2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)

2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)

Table of contents

A versatile structural analysis method for analog, digital and mixed-signal circuits

Enclosing the modeling error in analog behavioral models using neural networks and affine arithmetic

A case study: Automatic topology synthesis for analog circuit from an ASDeX specification

A prototype framework for conceptual design of novel analog circuits

An efficient linear-time variant simulation technique of oscillator phase sensitivity function

UVM-based verification of smart-sensor systems

A CAD framework for the characterization and use of memristor models

AIDA: Automated analog IC design flow from circuit level to layout

Automated analog filter pair design on the basis of a gyrator-capacitor prototype circuit realised in SI technique

Optimization of fully-integrated power converter circuits comprising tapered inductor layout and temperature effects

Surrogate models of Pareto-optimal planar inductors

Synthesis of compact planar inductors in LTCC technology

A high bandwidth 11-bit 1.5GS/s track and hold amplifier in 0.25 µm SiGe BiCMOS

Analysis of bias-shift effects in free-running and injection-locked negative resistance oscillators

Augmenting slicing trees for analog placement

LDS based tools to ease template construction

Multi-objective multi-constraint routing of analog ICs using a Modified NSGA-II Approach

Temperature sensor placement including routing overhead and sampling inaccuracies

An automated layout-aware design flow

Systematic generation of performance models of reconfigurable analog circuits

An integrated MEG acquisition system with CMOS instrumentation amplifier and offset cancellation

Design considerations on CMOS bulk-driven differential input stages

EKV-based method for biasing CMOS analog cells using mUltiple-Inputs Floating Gate MOSFETs

Modeling switching losses in MOSFETs half-bridges

Modeling, simulation and hardware implementation of a Lundell Machine controller circuit with three-phase inverter bridge

An improved design of VCCS-based active inductors

New jerk circuits with mixed-mode oscillations

Electromechanical performance comparison for different CMUT element geometries

Hierarchical model-order reduction for robust design of parameter-varying systems

Schematic driven MEMS design

A novel software environment for design and simulation of piezoMEMS

Modeling carbon nanotube transistors using neural networks approach

Analysis and experimental verification of the sensitivity of PV cell model parameters

PSO-based charge pump chip area minimization

Analysis of SRAM cell characteristics based on high-k metal-gate strained Si/Si1−xGex MOSFET with consideration of NBTI/PBTI

Low power and robust 8T/10T subthreshold SRAM cells

Implementation of the dissection theorem in cadence virtuoso

SCALES - A behavioral simulator for pipelined analog-to-digital converter design

Current density aware algorithm for net generation in analog high current application

A multi-physics model of an IPMC actuator in the electrical, chemical, mechanical and thermal domains

Modeling in Verilog-AMS of a front-end for the design of a multichannel readout ASIC for Si microstrips

Model of a simple yet effective operational amplifier

Geometrical analysis of a MEMS microphone

Automatic common-centroid layout generation for binary-weighted capacitors in charge-scaling DAC

Frequency response of variants of a cantilever beam

A fully automated design flow for planar inductors

System-level time-domain behavioral baseband modeling of RF blocks for mixed-signal simulation

LC-VCO design methodology based on evolutionary algorithms

Performance evaluation of a class E power amplifier loaded by a high-isolation duplexer

EM-based design optimization of microstrip lines traversing a rectangular gap in the reference plane

Volterra series analysis of down-conversion CMOS mixer with high IIP2 and IIP3

Determining the dominant nonlinear contributions in a multistage op-amp in a feedback configuration

Frequency analysis of switched capacitor circuits

Analyzing nonlinear circuits using a modified harmonic balance method

Scalable parallel event-driven HDL simulation for multi-cores

A formal equivalence checking methodology for Simulink and Register Transfer Level designs

Inter-process communication energy estimation through AADL modeling

Transient computation of DC-DC converters using a new envelope following method

A nonlinear circuit model for a three BAW resonator filter working at high power level

Generation of the coupling circuit parameters for the coupled oscillators used in antenna arrays

Short-circuit-path and floating-node verification of analog circuits in power-down mode

Polynomial chaos based variability analysis of multiport systems

RELAB: A tool to include MOSFETs BTI and variability in SPICE simulators

Variability aware support vector machine based macromodels for statistical estimation of subthreshold leakage power

Modeling phase noise and jitter in subthreshold region and assessing the randomness performance of CMOS ring oscillators

Basic analog circuits with a-GIZO thin-film transistors: Modeling and simulation

Simple and accurate modeling of double-gate FinFET fin body variations

PERL scripts-based netlist analysis tool for the detection of ESD “big buffer” configurations

Background offset and gain calibration for time-interleaved ADC using digital sinusoidal calibration signal

Identification of systems for modelling and diagnosis based on a double multi-valued neural network

Automatic inspection of SET sensitivity in analog cells

High level simulations of real-time built-in self-test of Σ-Δ A/D converters

A cad tool for automatic formulation of symbolic state equations of oscillating circuits

A circuit synthesis technique based on network determinant expansion

Enclosing the modeling error in analog behavioral models using neural networks and affine arithmetic

Content Provider	IEEE Xplore Digital Library
Author	Krause, A. Olbrich, M. Barke, E.
Copyright Year	2012
Description	Author affiliation: Institute of Microelectronic Systems, Leibniz Universität Hannover, Germany (Krause, A.; Olbrich, M.; Barke, E.)
Abstract	One all-time challenge in behavioral modeling is to minimize the modeling error while still profiting from a simplified representation of an analog circuit. In many cases the modeling error is known, but up to now it was only an indicator for the quality of the model. Its influence on errors during simulation could not be evaluated. We present a flow for the generation of behavioral models based on neural networks which uses affine arithmetic to guarantee enclosing the modeling error. We also demonstrate that the approach can also be applied to modeling the effects of parameter deviations.
Starting Page	5
Ending Page	8
File Size	260487
Page Count	4
File Format	PDF
ISBN	9781467306850
e-ISBN	9781467306867
DOI	10.1109/SMACD.2012.6339403
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-09-19
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Analytical models Neurons Neural networks Transfer functions Data models Mathematical model Integrated circuit modeling
Content Type	Text
Resource Type	Article

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