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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Toyama, M. Uematsu, Y. Yorita, C. Osaka, H. |
| Copyright Year | 2015 |
| Description | Author affiliation: R&D Group, Hitachi, Ltd., Yokohama, Japan (Toyama, M.; Uematsu, Y.; Yorita, C.; Osaka, H.) |
| Abstract | System in package with glass interposers have been proposed to enable continuing improvements in communication performance and computing performance. One issue posed by glass interposers is the plane resonance resulting from low dielectric loss. This paper proposes a ground plane resonance suppression technique suitable for glass interposers using resistive vias. Placing high resistivity vias at each corner of plane effectively suppresses resonance. The optimal resistance is at the inflection point of the resonance frequency, or around 5 ohm for a 30 mm square glass interposer. |
| Starting Page | 449 |
| Ending Page | 450 |
| File Size | 105419 |
| Page Count | 2 |
| File Format | |
| e-ISBN | 9781479988976 |
| DOI | 10.1109/APCAP.2015.7374445 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-06-30 |
| Publisher Place | Indonesia |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Resistance Glass interposer Resonant frequency Dielectric losses System in Package Glass Conductivity Silicon 2.5-D integration |
| Content Type | Text |
| Resource Type | Article |
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