NDLI: Applications of a CMOS current squaring circuit in analog signal processing

Content Provider	IEEE Xplore Digital Library
Author	Saatlo, A.N. Ozoguz, S. Minaei, S.
Copyright Year	2015
Description	Author affiliation: Dept. of Electr.-Electron. Eng., Urmia Azad Univ., Urmia, Iran (Saatlo, A.N.) \|\| Electron. & Commun. Eng. Dept., Dogus Univ., Istanbul, Turkey (Minaei, S.) \|\| Fac. of Electr.-Electron., Istanbul Tech. Univ., Istanbul, Turkey (Ozoguz, S.)
Abstract	Applications of a CMOS squaring circuit in analog signal processing is studied in this paper. The circuit is based on the dual translinear loop and square-law characteristic of MOS transistor in saturation region. The reconfigurable circuit is employed as a basic analog cell for the implementation of several building blocks including multiplier, logarithmic, divider and exponential function generator circuits. It is proposed a solution for implamentation of the analog logarithmic and exponential functions, which are not an easily accessible characteristic in CMOS technology, as well as their integration in a configurable cell. Current-mode implementation of the circuits leads to straightforward and intuitive configurations. To study the performance of the circuit, effects of channel-length modulation as well as the mismatch in the threshold voltages are thoroughly discussed. The proposed circuits are designed and simulated using HSPICE simulator by level 49 parameters (BSIM3v3) in 0.35 μm standard CMOS technology. MATLAB results validate the simulation results which are obtained by HSPICE.
Starting Page	339
Ending Page	343
File Size	367337
Page Count	5
File Format	PDF
e-ISBN	9781479984985
DOI	10.1109/TSP.2015.7296280
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-07-09
Publisher Place	Czech Republic
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFET CMOS Simulation Basic cell Analog signal processing Signal processing CMOS technology Threshold voltage CMOS integrated circuits Squaring circuit Exponential function
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in