NDLI: TCAD simulation study of independent gate junctionless FET-based flash memory

Content Provider	IEEE Xplore Digital Library
Author	Srinivasan, R. Ambika, R.
Copyright Year	2012
Description	Author affiliation: Dept of IT, SSN College of Engineering, Kalavakkam - 603110, India (Srinivasan, R.) \|\| Dept of ECE, SSN College of Engineering, Kalavakkam - 603110, India (Ambika, R.)
Abstract	In this paper, typical floating gate flash memory is simulated and studied using independent gate junction-less FET. TCAD simulator is used for generating the memory structure as well as for studying its programming, erasing and reading behaviour. Programming and erasing delays are 1.6 ms and 1.53 ms respectively for 25 nm fin width device. Programming and erasing voltages are +9 V and −15 V respectively. It has been observed that higher fin width devices show lesser delay. Out of the two control gates one is used for programming, erasing and reading operations. The other control gate is used to modulate the programmed and erased threshold voltages during reading operation. The difference between the programmed and erased cell is independent of the bias applied at the other control gate.
Starting Page	738
Ending Page	740
File Size	531972
Page Count	3
File Format	PDF
ISBN	9781467302111
e-ISBN	9781467302128
DOI	10.1109/ICCEET.2012.6203927
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-21
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Performance evaluation TCAD Logic gates Threshold voltage Nanoscale devices JUNCTION-LESS FET THRESHOLD VOLTAGE FLASH MEMORY CHARGE
Content Type	Text
Resource Type	Article

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