NDLI: Triple well subthreshold CMOS logic using body-bias technique

Content Provider	IEEE Xplore Digital Library
Author	Niranjan, V. Kumar, A. Jain, S.B.
Copyright Year	2013
Description	Author affiliation: Dept. of Electron. & Commun. Eng., GGSIP Univ., New Delhi, India (Niranjan, V.; Kumar, A.; Jain, S.B.)
Abstract	Subthreshold logic provides extremely low power consumption since the power supplies are kept below the threshold voltage and using the small subthreshold current of MOS transistors to operate. Subthreshold circuits are ideal for ultra low power applications however they suffer from low operating speeds. By improving the speed of subthreshold circuits their application spectrum can be expanded. In this paper a body-bias technique in triple well CMOS technology is explored to match the subthreshold currents of both the NMOS and PMOS transistors for improving the speed of subthreshold circuits. We derive an approximate expression for the generated body bias voltage. Circuit simulations were conducted using 180nm CMOS technology to validate proposed concept. The results were compared with standard body bias technique in terms of delay and power consumption. The proposed body biasing technique improves power-delay product by approx. 38%.
Starting Page	1
Ending Page	6
File Size	377736
Page Count	6
File Format	PDF
e-ISBN	9781467361903
DOI	10.1109/ISPCC.2013.6663447
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-09-26
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFET Subthreshold logic Body bias Capacitance CMOS technology Threshold voltage Inverters CMOS integrated circuits Low power Triple well CMOS process
Content Type	Text
Resource Type	Article

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