NDLI: Congestion mitigation using flexible router architecture for Network-on-Chip

Content Provider	IEEE Xplore Digital Library
Author	Sayed, M.S. Shalaby, A. Ragab, M.E.-S. Goulart, V.
Copyright Year	2012
Description	Author affiliation: ECE Department, Egypt-Japan University of Science and Technology (E-JUST), Alexandria, Egypt (Sayed, M.S.; Shalaby, A.; Ragab, M.E.-S.; Goulart, V.)
Abstract	An important topic in Network-on-Chip (NoC) design is the tradeoff between area and performance. Some techniques tend to increase the number of buffers to improve performance. However this method increases the chip area and so does the power consumption. In this paper we introduce a new flexible router architecture that can improve the performance of the overall network using the same amount of buffering available but in an efficient way. Therefore there is no need to increase the size of buffers or to use extra virtual channels (VCs) which have high power and area overheads or complex logic. If there is a request to a busy buffer the router will store the incoming packet in any other suitable free buffer in the router. The Flexible router shows an increase in performance in terms of increasing the saturation rate for Hotspot, Uniform, and Nearest-Neighbor traffics, especially Hotspot with 11.4% increase. Discussion about area overhead over a standard Base router and the analysis of arriving unordered packets (side-effect) are also presented.
Starting Page	182
Ending Page	187
File Size	195969
Page Count	6
File Format	PDF
ISBN	9781467304856
e-ISBN	9781467304849
DOI	10.1109/JEC-ECC.2012.6186980
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-06
Publisher Place	Egypt
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computers Buffer storage System recovery Traffic control Routing Throughput Delay
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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