NDLI: EQU-IITG: A multi-format formal equivalence checker

Content Provider	IEEE Xplore Digital Library
Author	Mishra, A.K. Chandra, A.
Copyright Year	2011
Description	Author affiliation: Department of Electrical Engineering, University of Cape Town, Cape Town, South Africa (Mishra, A.K.) \|\| Patent Research Services in CPA Global Support Services (Chandra, A.)
Abstract	Checking for the functional equivalence between two models of a design is a crucial step in a hierarchical transformation based design flow, in which a designer obtains low level implementation models by manual or automatic translation from higher level specification models. Some of the most difficulty tasks CAD users face are the evaluation, comparison and compatibility-issue for different formats of different EDA tools and algorithms. It is vital to understand how well a given verification tool does the required job and which of the many possible formats can be verified. Formal methods are playing a major role in the verification environment. This paper presents a verification technique for functional comparison of large circuits (combinational and sequential) using a combination of known approaches. The idea is based on the tight integration of structural satisfiability (SAT) solver, BDD sweeping, FSM traversal and random simulation; all four working on a shared graph representation of the circuit. This integral method enhances the performance of BDD verification based on the complexity of the circuit. Further, the random simulation algorithm works on the compressed circuit graph and thus runs more efficiently. The outlined approach is effective for both sequential and combinational circuits. Besides this verification, this tool supports multiple formats for verification, generated through the different stages of design flow. This avoids requirement of another tool for conversion of one format to the other for equivalence checking.
Starting Page	1
Ending Page	6
File Size	400042
Page Count	6
File Format	PDF
ISBN	9781467301374
e-ISBN	9781467301367
DOI	10.1109/ICEAS.2011.6147138
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-12-28
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Boolean functions Benchmark testing Logic gates Data structures Complexity theory Combinational circuits Integrated circuit modeling
Content Type	Text
Resource Type	Article

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