NDLI: Delay modelling of on-chip RC global VLSI interconnect for step input

Content Provider	IEEE Xplore Digital Library
Author	Maheshwari, V. Bhadauna, R.S. Jha, S.K. Kar, R. Mandai, D. Bhattacharjee, A.K.
Copyright Year	2012
Description	Author affiliation: Deptt of ECE, National Institute of Technology, Durgapur W.B, INDIA (Jha, S.K.; Kar, R.; Mandai, D.; Bhattacharjee, A.K.) \|\| Deptt of ECE, Apeejay Stya University, Gurgaon, Haryana, India (Maheshwari, V.) \|\| Deptt of ECE, Institute of Engineering and Technology, Agra, U.P., India (Bhadauna, R.S.)
Abstract	This paper presents an accurate and efficient model to compute the delay metric of on chip high speed VLSI interconnects. The proposed delay metric assumption is based on RC interconnect model. Interconnect has become a dominant factor in deep sub micrometer (DSM) integrated circuit (IC) technology. The Elmore delay has been the metric of choice for the performance driven design applications. But the accuracy of the Elmore delay is insufficient. For optimization like physical synthesis and static timing analysis, efficient interconnect delay computation is critical. In this paper, a delay metric using RC-int and RC-out has been formulated which computes the delay at any arbitrary point on the waveform and at any point along the interconnect line. The proposed model is based on the first three moments of the impulse response. Two pole RC model is developed based on the first, second and third moments' effect onto the delay calculation for interconnect lines. This two pole approach permits the pre-characterization of the interconnect delay. The empirical D3M metric is shown to be a special case. The proposed metric also provides an expression for impulse response. The SPICE simulation results justify the accuracy and efficacy of the proposed model.
Starting Page	458
Ending Page	463
File Size	344275
Page Count	6
File Format	PDF
ISBN	9781467348065
e-ISBN	9781467348058
DOI	10.1109/WICT.2012.6409121
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-10-30
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decision support systems Step Input VLSI Delay Modelling RC Line Communications technology On-Chip Interconnect
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in