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Learning-based approximation of interconnect delay and slew in signoff timing tools

Content Provider	IEEE Xplore Digital Library
Author	Kahng, A.B. Seokhyeong Kang Hyein Lee Nath, S. Wadhwani, J.
Copyright Year	2013
Description	Author affiliation: ECE Depts., Univ. of California at San Diego, La Jolla, CA, USA (Seokhyeong Kang; Hyein Lee; Wadhwani, J.) \|\| CSE Depts., Univ. of California at San Diego, La Jolla, CA, USA (Kahng, A.B.; Nath, S.)
Abstract	Incremental static timing analysis (iSTA) is the backbone of iterative sizing and Vt-swapping heuristics for post-layout timing recovery and leakage power reduction. Performing such analysis through available interfaces of a signoff STA tool brings efficiency and functionality limitations. Thus, an internal iSTA tool must be built that matches the signoff STA tool. A key challenge is the matching of “black-box” modeling of interconnect effects in the signoff tool, so as to match wire slew, wire delay, gate slew and gate delay on each arc of the timing graph. Previous moment-based analytical models for gate and wire slew and delay typically have large errors when compared to values from signoff STA tools. To mitigate the accumulation of these errors and preserve timing correlation, sizing tools must invoke the signoff STA tool frequently, thus incurring large runtime costs. In this work, we pursue a learning-based approach to fit analytical models of wire slew and delay to estimates from a signoff STA tool. These models can improve the accuracy of delay and slew estimations, such that the number of invocations of the signoff STA tool during sizing optimizations is significantly reduced.
Starting Page	1
Ending Page	8
File Size	328363
Page Count	8
File Format	PDF
ISBN	9781467361736
DOI	10.1109/SLIP.2013.6681682
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-06-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Analytical models Correlation Computational modeling Wires Logic gates Delays
Content Type	Text
Resource Type	Article

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