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  1. Workshop on Architecture and Multi-Core Applications (WAMCA).
  2. 2011 Second Workshop on Architecture and Multi-Core Applications (wamca 2011)
  3. Economical Two-fold Working Precision Matrix Multiplication on Consumer-Level CUDA GPUs
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2012 Third Workshop on Applications for Multi-Core Architecture
2011 Second Workshop on Architecture and Multi-Core Applications (wamca 2011)
Copyright Page
Table of Contents
Message from the Program Chairs
Committees
Keynote
Industrial Talks
Tutorial
Large Scale Kronecker Product on Supercomputers
Trace-Based Visualization as a Tool to Understand Applications' I/O Performance in Multi-core Machines
Adaptive Power Optimization of On-chip SNUCA Cache on Tiled Chip Multicore Architecture Using Remap Policy
Evaluating the Problem of Process Mapping on Network-on-Chip for Parallel Applications
Economical Two-fold Working Precision Matrix Multiplication on Consumer-Level CUDA GPUs
Author index
Publisher's Information

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Economical Two-fold Working Precision Matrix Multiplication on Consumer-Level CUDA GPUs

Content Provider IEEE Xplore Digital Library
Author Fujimoto, N.
Copyright Year 2011
Abstract Dot product faithfully rounded after "as if" computed in $K$-fold working precision (K>=2)is known to be computable only with floating-point numbers defined in IEEE 754 floating-point standard.This paper presents a CUDA GPU implementation of two-fold working precision matrix multiplication based on the dot product computation method.Experimental results on a GeForce GTX580 and a GTX560Ti show that the proposed implementation has 1.84 to 1.95 timeshigher GFLOPS performance in two-fold working precision compared to the performance of CUBLAS dgemm in double-precision on a Tesla C2070 high-end GPU.The proposed implementation can be used to obtain higher performance in pseudo double-precision with low cost consumer-level GPUs whose double-precision native performance is limited.
Starting Page 24
Ending Page 29
File Size 306811
Page Count 6
File Format PDF
ISBN 9781467302210
e-ISBN 9780769546131
DOI 10.1109/WAMCA.2011.18
Language English
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date 2011-10-26
Publisher Place Brazil
Access Restriction Subscribed
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword CUDA Matrix multiplication Instruction sets Memory management Documentation Programming Error free transformation GPGPU Graphics processing unit Clocks
Content Type Text
Resource Type Article
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