NDLI: Making digital systems design more convenient to students by means of visualization

Content Provider	IEEE Xplore Digital Library
Author	Jelemenska, K.
Copyright Year	2013
Description	Author affiliation: Fac. of Inf. & Inf. Technol., Slovak Univ. of Technol. in Bratislava, Bratislava, Slovakia (Jelemenska, K.)
Abstract	Thanks to the ever-growing complexity of contemporary digital systems the HDLs (Hardware Description Languages) and EDA (Electronic Design Automation) tools have became an inevitable part of the digital design process. To make the HDL model's complexity better manageable graphical representation of its structure is often required. Also to browse the models' extensive simulation results the proper representation is needed especially for students and beginners. In this contribution the visualization methods for digital systems models' structure and simulation results have been proposed. The methods covering the most widely used HDLs - namely Verilog, VHDL, and SystemC, have been integrated into the visualization framework allowing to visualize and browse the model's structure on all hierarchical levels, enabling also to visualize simulation results directly in the displayed structure. Thanks to the adoption of unified formats to represent models' structure and simulation results the framework can be extended to support other HDLs. However, the simulation results can also be displayed in the traditional waveform style to improve the verification capability.
Starting Page	183
Ending Page	188
File Size	552814
Page Count	6
File Format	PDF
e-ISBN	9781479921621
DOI	10.1109/ICETA.2013.6674426
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-24
Publisher Place	Slovakia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Structure visualization Hardware description languages Digital system modeling Model verification
Content Type	Text
Resource Type	Article

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