NDLI: Neuronal Logic gates realization using Vedic mathematics

Content Provider	IEEE Xplore Digital Library
Author	Anshika Yamuna, S.V. Goel, N. Indu, S.
Copyright Year	2015
Description	Author affiliation: Dept. of Electron. & Commun. Eng., Delhi Technol. Univ., Delhi, India (Anshika; Yamuna, S.V.; Goel, N.; Indu, S.)
Abstract	Gates are the fundamental building block of all logic circuits. Artificial neural networks (ANN) have processing capabilities in a parallel architecture, and due to this they are useful in applications like pattern recognition, system identification, prediction problems, robotics, and control problems. Boolean logic realization using artificial neural network is known as Neuronal Logic. Simple and low precision computations are the basic requirements of ANN which can be performed faster. This can be implemented on cheap and low precision hardware. Neural network involves enormous number of multiplication and addition calculations. It has been already proved that multipliers based on Vedic mathematics are faster in speed than the standard multipliers. In this paper, the possibility of hardware realization of neuronal logic gates using Vedic multipliers herein referred to as Vedic neuron has been explored. This is achieved by performing the neural network computations using Vedic mathematics rather than the conventional multiplication process. Basic logic gates like AND, OR and AND-NOT have been studied and its hardware implementation using neural network has been simulated using VHDL. A comparative study was carried out on the computation speed of neuronal logic gates implemented using conventional multipliers as well as neuronal logic gates implemented using Vedic multipliers. The increase in processing speed with Vedic neuron implementation has been observed which can be of use in several real time operations where speed is critical.
Starting Page	540
Ending Page	545
File Size	1790120
Page Count	6
File Format	PDF
e-ISBN	9781467368094
DOI	10.1109/NGCT.2015.7375178
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-09-04
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Neuronal Logic Vedic multiplication FPGA Urdhva Tiryagbhyam Mathematics Biology ALU Pattern recognition Table lookup Logic gates Hardware Real-time systems Artificial neural network
Content Type	Text
Resource Type	Article

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