NDLI: Comparison of hardware accelerators for some ALICE online computing applications

Content Provider	IEEE Xplore Digital Library
Author	Changaival, B. Bouron, D. Chapeland, S. Achalakul, T.
Copyright Year	2015
Description	Author affiliation: ALICE DAQ Team, CERN, Geneva, Switzerland (Chapeland, S.) \|\| Comput. Eng., EPITA, Paris, France (Bouron, D.) \|\| Comput. Eng., KMUTT, Bangkok, Thailand (Changaival, B.; Achalakul, T.)
Abstract	ALICE (A Large Ion Collider Experiment) is an experiment which studies about interacting matter and the quark-gluon plasma at the European Organization for Nuclear Research (CERN) Large Hadron Collider (LHC). Due to the detector upgrade in 2018, 1TB/s data are expected to flow from the detector and the computing system needs to process these data online. To speed up the online processing, different hardware accelerators must be tested thoroughly to see whether they are suitable for the tasks. In this paper, we propose a benchmark method for the ALICE $O^{2}$ project on various accelerators. There are three targeted computing platform for benchmark, namely, Graphics Processing Unit (GPU), Many-Integrated Core (MIC), and Accelerated Processing Unit (APU). For completeness, CUDA, OpenMP and OpenCL were used to implement the selected algorithms, which correspond to some of the real processing tasks to be implemented for ALICE. The initial results together with the discussion on algorithm optimizations and hardware limitations are also presented.
Starting Page	21
Ending Page	26
File Size	787881
Page Count	6
File Format	PDF
e-ISBN	9781467367226
DOI	10.1109/ICSECS.2015.7333117
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-08-19
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	OpenMP Graphics processing units Many-Integrated Core Graphics Processing Unit Circular Hough Transform Accelerated Processing Unit CUDA Microwave integrated circuits Clustering algorithms Detectors Benchmark testing Central Processing Unit OpenCL Acceleration Accelerator
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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