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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Machida, T. Yamamoto, D. Iwamoto, M. Sakiyama, K. |
| Copyright Year | 2014 |
| Description | Author affiliation: Fujitsu Labs. Ltd., Kawasaki, Japan (Yamamoto, D.) || Univ. of Electro-Commun., Chofu, Japan (Machida, T.; Iwamoto, M.; Sakiyama, K.) |
| Abstract | Arbiter-based Physically Unclonable Function (PUF) is one kind of the delay-based PUFs that use the time difference of two delay-line signals. One of the previous work suggests that Arbiter PUFs implemented on Xilinx Virtex-5 FPGAs generate responses with almost no difference, i.e. with low uniqueness. In order to overcome this problem, Double Arbiter PUF was proposed, which is based on a novel technique for generating responses with high uniqueness from duplicated Arbiter PUFs on FPGAs. It needs the same costs as 2-XOR Arbiter PUF that XORs outputs of two Arbiter PUFs. Double Arbiter PUF is different from 2-XOR Arbiter PUF in terms of mode of operation for Arbiter PUF: the wire assignment between an arbiter and output signals from the final selectors located just before the arbiter. In this paper, we evaluate these PUFs as for uniqueness, randomness, and steadiness. We consider finding a new mode of operation for Arbiter PUF that can be realized on FPGA. In order to improve the uniqueness of responses, we propose 3-1 Double Arbiter PUF that has another duplicated Arbiter PUF, i.e. having 3 Arbiter PUFs and output 1-bit response. We compare 3-1 Double Arbiter PUF to 3-XOR Arbiter PUF according to the uniqueness, randomness, and steadiness, and show the difference between these PUFs by considering the mode of operation for Arbiter PUF. From our experimental results, the uniqueness of responses from 3-1 Double Arbiter PUF is approximately 50%, which is better than that from 3-XOR Arbiter PUF. We show that we can improve the uniqueness by using a new mode of operation for Arbiter PUF. |
| Starting Page | 871 |
| Ending Page | 878 |
| File Size | 832242 |
| Page Count | 8 |
| File Format | |
| ISBN | 9788360810583 |
| ISSN | 23005963 |
| DOI | 10.15439/2014F140 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-09-07 |
| Publisher Place | Poland |
| Access Restriction | Subscribed |
| Rights Holder | Polish Information Processing Society |
| Subject Keyword | Wires Organizations Delays Electronic mail Hamming weight Field programmable gate arrays |
| Content Type | Text |
| Resource Type | Article |
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