NDLI: Adaptive estimation and compensation of the time delay in a periodic non-uniform sampling scheme

Content Provider	IEEE Xplore Digital Library
Author	Vernhes, J.-A. Chabert, M. Lacaze, B. Lesthievent, G. Baudin, R. Boucheret, M.-L.
Copyright Year	2015
Description	Author affiliation: Thales Alenia Space, Toulouse, France (Baudin, R.) \|\| CNES, Toulouse, France (Lesthievent, G.) \|\| INP-ENSEEIHT/IRIT, Univ. de Toulouse, Toulouse, France (Vernhes, J.-A.; Chabert, M.; Boucheret, M.-L.) \|\| TeSA, Toulouse, France (Lacaze, B.)
Abstract	High sampling rate Analog-to-Digital Converters (ADCs) can be obtained by time-interleaving low rate (and thus low cost) ADCs into so-called Time-Interleaved ADCs (TI-ADCs). Nevertheless increasing the sampling frequency involves an increasing sensibility of the system to desynchronization between the different ADCs that leads to time-skew errors, impacting the system with non linear distortions. The estimation and compensation of these errors are considered as one of the main challenge to deal with in TI-ADCs. Some methods have been previously proposed, mainly in the field of circuits and systems, to estimate the time-skew error but they mainly involve hardware correction and they lack of flexibility, using an inflexible uniform sampling reference. In this paper, we propose to model the output of L interleaved and desynchronized ADCs with a sampling scheme called Periodic Non-uniform Sampling of order L (PNSL). This scheme has been initially proposed as an alternative to uniform sampling for aliasing cancellation, particularly in the case of bandpass signals. We use its properties here to develop a flexible on-line digital estimation and compensation method of the time delays between the desynchronized channels. The estimated delay is exploited in the PNSL reconstruction formula leading to an accurate reconstruction without hardware correction and without any need to adapt the sampling operation. Our method can be used in a simple Built-In Self-Test (BIST) strategy with the use of learning sequences and our model appears more flexible and less electronically expensive, following the principles of “Dirty Radio Frequency” paradigm: designing imperfect analog circuits with subsequently digital corrections of these imperfections.
Starting Page	473
Ending Page	477
File Size	585735
Page Count	5
File Format	PDF
ISBN	9781467373531
DOI	10.1109/SAMPTA.2015.7148936
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Conferences Estimation Built-in self-test Signal processing Hardware Delays Calibration
Content Type	Text
Resource Type	Article

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