NDLI: System power noise analysis using modulated CPM

Content Provider	IEEE Xplore Digital Library
Author	Di Hu Yongxue Yu Ferrario, A. Bayet, O. Lin Shen Nimmagadda, R. Bonardi, F. Matus, F.
Copyright Year	2015
Description	Author affiliation: STMicroelectron., Cisco Syst., San Jose, CA, USA (Di Hu; Yongxue Yu; Ferrario, A.; Bayet, O.; Lin Shen; Nimmagadda, R.; Bonardi, F.; Matus, F.)
Abstract	As the semiconductor industry advances to ever smaller technology nodes, the power distribution network (PDN) is becoming an essential design factor to ensure system performance and reliability. The time domain simulations typically utilize the chip power model (CPM), generated by Ansys RedHawk, as the current load. The typical CPM only includes current consumption in a few clock cycles, which includes the high frequencies components (several hundreds of MHz), but losing mid to low frequencies. This paper describes a modulated CPM (MCPM) design and signoff process for PDN. The first step is frequency domain analysis of PDN to identify the die-package resonance frequency. Then the chip gate level simulation is performed over an extended period of time to generate the VPD (Value Change Dump plus) file, with realistic low to mid frequency current components. This information is then used to modulate the CPM as the current load for the system level time domain noise simulations. This PI analysis flow was validated using a set of three test cases, with reasonable simulation-measurement correlation achieved. This analysis flow enables more effective power/ground plane layout optimization and capacitor optimization in a timely manner.
Starting Page	265
Ending Page	270
File Size	1382533
Page Count	6
File Format	PDF
ISBN	9781479919925
e-ISBN	9781479919932
DOI	10.1109/EMCSI.2015.7107697
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-03-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Measurement Voltage measurement Correlation Noise Capacitor optimization VPD Noise measurement Voltage control Time-domain analysis Power integrity PCB Simulation MCPM Package Impedance Load modeling
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Power integrity chip-package-PCB co-simulation for I/O interface of DDR3 high-speed memory

Noise driven in-package decoupling capacitor optimization for power integrity

Induction Machine Modeling for Distribution System Analysis using Initialization and Time-Domain Methods

Signal-power integrity co-simulations of high speed systems via chip-package-PCB co-analysis methodology

A new confirmation of voltage collapse via instantaneous time domain simulation

Extended CPM for system power integrity analysis

Power Integrity in Silicon-Package-Board Codesign Flow

A time domain load modelling technique and harmonics analysis

Particle swarm optimization applied in power system measurement-based load modeling

System power noise analysis using modulated CPM

Similar Documents

Power integrity chip-package-PCB co-simulation for I/O interface of DDR3 high-speed memory

Noise driven in-package decoupling capacitor optimization for power integrity

Induction Machine Modeling for Distribution System Analysis using Initialization and Time-Domain Methods

Signal-power integrity co-simulations of high speed systems via chip-package-PCB co-analysis methodology

A new confirmation of voltage collapse via instantaneous time domain simulation

Extended CPM for system power integrity analysis

Power Integrity in Silicon-Package-Board Codesign Flow

A time domain load modelling technique and harmonics analysis

Particle swarm optimization applied in power system measurement-based load modeling

System power noise analysis using modulated CPM