NDLI: A modified variation-tolerant keeper architecture for evaluation contention & leakage current minimization for wide fan-in domino structures

Content Provider	IEEE Xplore Digital Library
Author	Patnaik, S. Hari, U. Ahuja, M. Narang, S.
Copyright Year	2015
Description	Author affiliation: Dept. of Electron. & Telecommun., NMIMS Univ., Mumbai, India (Patnaik, S.; Hari, U.; Ahuja, M.; Narang, S.)
Abstract	The effects of process variation exacerbates as we keep on aggressively scaling the device dimensions. Register files composed using domino logic structures are a crucial block in the critical path of the microprocessors and the adverse effects of process variations on these could lead to functional failure in a worst case scenario. Erroneous behaviour of circuits can give rise to high and varying power consumption and can prove to be expensive. To deal firmly with the adverse effects of process variations with the goal of reduced leakage current, feedback keeper architecture has been proposed in this paper. This keeper architecture adapts itself to the changing conditions and the circuit's performance metrics do not vary much even at the extreme process corners (SS to FF). Though the proposed keeper architecture incurs an area overhead of 16%, it provides high tolerance and reduces power consumption by nearly 42% at FF corner and by 32% at SS corner with respect to other existing designs. The reduction in the leakage current and evaluation contention are about 95% & 84% when compared to standard domino gate with footless scheme. All the simulations have been performed at 45nm & 32nm technologies on a host of domino logic circuits ranging from a 64:1 multiplexer to 32-bit comparator circuitry at using BSIM 4v4.7 model in SILVACO EDA tool at an operating frequency of 1.2 GHz.
Starting Page	1
Ending Page	7
File Size	356866
Page Count	7
File Format	PDF
e-ISBN	9781479970759
DOI	10.1109/ICCPCT.2015.7159348
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-03-19
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power demand Multiplexer Computer architecture Logic gates Leakage current Delays Process variation Transistors Leakage currents Integrated circuit modeling
Content Type	Text
Resource Type	Article

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