NDLI: Mission critical software test philosophy a SILS based approach in Indian Mars Orbiter Mission

Content Provider	IEEE Xplore Digital Library
Author	Sumith Shankar, S. Desai, Kiran Dutta, Shuvo Chetwani, Rajiv R. Ravindra, M. Bharadwaj, K.M.
Copyright Year	2014
Description	Author affiliation: Software Quality Assurance Division - Systems Reliability Group ISRO Satellite Centre (ISAC), Bangalore 560017, India (Sumith Shankar, S; Desai, Kiran; Dutta, Shuvo; Chetwani, Rajiv R; Ravindra, M.; Bharadwaj, K.M.)
Abstract	ISRO Satellite Centre (ISAC) is the lead centre of the Indian Space Research Organisation in the development and operationalisation of satellites for communication, navigation and remote sensing applications. In all these spacecrafts, highly advanced embedded systems carryout variety of mission critical functions. Each of these embedded systems house heterogeneous Processor and Embedded Software Combinations to carry out their functionalities. As per existing practices, testing of on board software to confirm its functioning takes place only when the software is integrated with its associated hardware. On the contrary, by a technique called the Software in Loop Simulation (SILS) test method, the on-board software can be fully tested in a software simulated dynamic environment without Hardware. This method of flight software validation is demonstrated in MARS ORBITER MISSION for AOCE, TCP, SSR, BDH software. The results very well demonstrate the effectiveness of the technique in early performance prediction and assessment of on-board software. This validation philosophy will be followed for all future spacecrafts. In a development environment where software requirements are too complex and requirement changes are to be incorporated even during final stages of development, this technique offers an excellent solution in fully validating on board software at source code level before it gets integrated with target hardware. This additional validation step not only improves software quality but also enhances productivity and reduces system turnaround time.
Starting Page	414
Ending Page	419
File Size	24303268
Page Count	6
File Format	PDF
ISBN	9781479966295
DOI	10.1109/IC3I.2014.7019637
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-11-27
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Software In loop simulation Validation Automation Verification Informatics Simulator
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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