NDLI: Hardware implementation of NB PHY baseband transceiver for IEEE 802.15.6 WBAN

Content Provider	IEEE Xplore Digital Library
Author	Mathew, P. Augustine, L. Kushwaha, D. Vivian, D. Selvakumar, D.
Copyright Year	2014
Description	Author affiliation: UCHR Group, CDAC, Bangalore, India (Kushwaha, D.; Vivian, D.; Selvakumar, D.) \|\| Intern, CDAC, Bangalore, India (Mathew, P.; Augustine, L.)
Abstract	This paper presents the FPGA implementation of Narrowband Physical Layer architecture for Wireless Body Area Network (WBAN) based on IEEE 802.15.6-2012 standard. An abstract level hardware implementation of the most matured Narrowband (NB) PHY operating at 2.4 GHz ISM band among the three PHY layers defined by the standard is proposed. Major building blocks of PHY transceiver such as CRC, spreader, interleaver and scrambler were individually designed and integrated. To avoid the inherent limitation of the data transmission and to achieve higher reliability especially for medical applications, BCH (63, 51, 2) encoder and decoder is integrated to the design. Before modulation, spreading technique is employed and supports pi/2 DBPSK modulation. The transceiver achieves a data rate of 121.4 kbps and packet size of 256 bits. The design has been simulated in Questa 10.1.d, synthesized in Xilinx ISE 14.4 and successfully implemented and tested on ML605 Evaluation Board through PCIe interface. The proposed design can interact with Microblaze processor and the board can be interfaced with Analog Devices FMC-Communication Board, AD-FCOMMS1-EBZ.
Starting Page	64
Ending Page	71
File Size	435880
Page Count	8
File Format	PDF
e-ISBN	9781479950973
DOI	10.1109/MedCom.2014.7005977
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-11-07
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Baseband BCH Receivers Transceivers Pi/2 DBPSK Decoding Niobium Wireless communication WBAN IEEE 802.15 Standards VHDL IEEE 802.15.6 NB PHY
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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