NDLI: General pattern identification of debugging system

Content Provider	IEEE Xplore Digital Library
Author	Falahah Suwardi, I.S. Surendro, K.
Copyright Year	2015
Description	Author affiliation: Inf. Dept., Univ. Widyatama, Indonesia (Falahah) \|\| Sch. of Electr. Eng. & Inf., Inst. Teknol. Bandung, Bandung, Indonesia (Suwardi, I.S.; Surendro, K.)
Abstract	Debugging is an important work in software development. Along with the increasing complexity of the software debugging process also becomes as simple as the original. This paper will discuss the generic pattern of debugging system. Vary approaches and algorithms that have been proposed to build a good debugger system and easily used by system developers. The bug can be the caused by internal or external sources. All debugger software is ideally fulfil 4 principle Heisenberg principle ie, truthful debugging, program context information system development and debugging trails. But actually not all debuggers can meet this requirement. Debugger also can classify in many ways such as source-level and machine-level, stand-alone and IDE, 4GL and 3GL, OS Kernel and Application Level, and Application-specific or in-circuit emulation. Debugger architecture can typically divide into 5 layers ie the user interface layer, the kernel layer, OS APIs, OS and CPU, before it touch the user program. Researchers also proposed many techniques in debugging methodologies such as Darwin, message oriented, backtracking approach, and concept assignment (CA). Implementation of CA opens new opportunities to a proposed new model of debugging that can leverage into a high level of software as a part of information system. The CA approach can implement According to the V-model of software development approach.
Starting Page	67
Ending Page	72
File Size	788487
Page Count	6
File Format	PDF
ISBN	9781509000951
e-ISBN	9781509000968
DOI	10.1109/ICTS.2015.7379873
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-09-16
Publisher Place	Indonesia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Context Debugger Techniques Concept assignment Debugging Computer architecture V-model Computer crashes Kernel General pattern
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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