NDLI: Radiation tolerant heterogeneous Multicore “system on chip” with built-in multichannel SpaceFibre switch for the “intelligent” signals and images processing systems

Content Provider	IEEE Xplore Digital Library
Author	Solokhina, T. Petrichkovich, J. Glushkov, A. Alekseev, I. Menshenin, L. Yuriy, S. Elena, S.
Copyright Year	2014
Description	Author affiliation: ELVEES RnD Center, Zelenograd, Russia (Solokhina, T.; Petrichkovich, J.; Glushkov, A.; Alekseev, I.; Menshenin, L.) \|\| Univ. of Aerosp. Instrum., St. Petersburg, Russia (Yuriy, S.; Elena, S.)
Abstract	The article presents a Radiation tolerant heterogeneous Multi-core ASIC MC-30SF6 as the SoC (System-on-Chip) for the onboard “intelligent” signals and images processing systems. MC-30SF6 based on a CMOS 180nm Radiation tolerant library and consists of the five ELVEES IP - cores for the processing and compression data with extra performance more than 9 GFLOPs. The SoC design and architecture support fault tolerance against SEU errors. SoC has built-in multichannel multiprotocol SpaceFibre/GigaSpaceWire (SpaceWire-RUS standard)/SpaceWire embedded networking subsystem. The networking subsystem provides multiple ports for high-rate interconnection with combination of SpaceWire/GigaSpaceWire/SpaceFibre links. SoC support four ports GigaSpaceWire/two ports SpaceWire switch. Input and processed data streams transmitted via 1.25 Gbps two multiprotocol SpaceFibre/GigaSpaceWire and four GigaSpaceWire links. Two SpaceWire links (ECSS-E-50-12C) provide data transfer bandwidth from 2 up to 400 Mbps. The MC-30SF6 embedded networking subsystem on the base SpaceWire/GigaSpaceWire/SpaceFibre provide a balance between ASIC throughput and SoC performance especially for the multifunctional micro and nanosatellites systems.
Starting Page	1
Ending Page	5
File Size	552749
Page Count	5
File Format	PDF
ISBN	9780955719653
DOI	10.1109/SpaceWire.2014.6936228
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-22
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	University of Dundee
Subject Keyword	Multicore processing Image processing Ports (Computers) Switches System-on-chip IP networks Multiprotocol SpaceFibre/GigaSpaceWire based links Radiation tolerant heterogeneous Multicore ASIC
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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