NDLI: Analysis of FXP adders and multipliers for speed- and area-efficient LNS arithmetic unit

Content Provider	IEEE Xplore Digital Library
Author	Ismail, Rizalafande Che Naziri, Siti Zarina Md Murad, Sohiful Anuar Zainol Coleman, J. N.
Copyright Year	2014
Description	Author affiliation: School of Electrical & Electronic Engineering, Newcastle University, NE1 7RU, United Kingdom (Coleman, J. N.) \|\| School of Microelectronic Engineering, Universiti Malaysia Perlis, 02600 Arau, Perlis, Malaysia (Ismail, Rizalafande Che; Naziri, Siti Zarina Md; Murad, Sohiful Anuar Zainol)
Abstract	This paper portrays the selection of hardware unit architectures to be implemented in the new LNS based on a 32bit system. The implementations of the LNS multiply and divide only require a FXP adder, while the LNS addition and subtraction function comprised of several memories, FXP adders and multipliers together with other supporting logics. Thus, in choosing the best FXP adders and multipliers, each of the arithmetic is functionally verified and synthesised using Synopsys Design Compiler in Faraday 0.18 µm CMOS technology based on a 32-bit system. Two types of performance measurement, which are the worst-case delay and the silicon area, are chosen as the evaluation arguments. From conducted analytical studies, the CLA/CSLA adder and Booth recoded with Wallace tree multiplier were the best FXP adder and multiplier blocks to be applied in the system since they were the fastest designs. Using these blocks, the synthesis of the LNS system produced an approximately 7.10 ns of critical delay for addition and subtraction, and solely 1.16 ns for multiplication and division. The total area for a complete LNS architecture was 599,871 $µm^{2},$ in which 65% the size of previously designed LNS architecture of ELM.
Starting Page	238
Ending Page	243
File Size	215781
Page Count	6
File Format	PDF
ISBN	9781479961030
DOI	10.1109/ICED.2014.7015806
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-08-19
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	LNS Hardware Silicon Delays CLA/CSLA adder Arrays Adders Booth recoded with Wallace tree multiplier Delay Total area FXP
Content Type	Text
Resource Type	Article

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