NDLI: On automated generation of checker units from hardware assertion languages

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2014 Microelectronic Systems Symposium (MESS)

Front cover

Title page

Preface

Program

Deterministic system design with Time-Triggered technology

On automated generation of checker units from hardware assertion languages

Electromagnetic emission simulation evaluation — A use case

Thermal actuated passive bistable MEMS switch

Thermal influences on driven damped MEMS cantilevers

Advances in triple junction photo diodes

Direct-digital time-domain oscillator stability measurement

Pretouch sensing of ferromagnetic materials for robot graspers

Modeling an omnidirectional fiber-optic strain transducer

Monitoring the glycerol concentration in aqueous glycerol solutions using a micromachined flow sensor

Concept study on an electrodynamically driven and read-out torsional oscillator

Optimizing the energy supply of autonomous wireless sensor nodes

RF-MEMS: A development flow driving innovative device concepts to high performance components and networks for wireless applications

High frequency Class-DE push/pull power amplifier utilizing a parallel compensation inductance

Using Linux in ARM-based industrial embedded systems — A survey

Committees

On automated generation of checker units from hardware assertion languages

Content Provider	IEEE Xplore Digital Library
Author	Fibich, C. Wenzl, M. Rossler, P.
Copyright Year	2014
Description	Author affiliation: Dept. of Embedded Syst., Univ. of Appl. Sci. Technikum Wien, Vienna, Austria (Fibich, C.; Wenzl, M.; Rossler, P.)
Abstract	This work investigates how assertion-based verification methods applied to simulations can also be used at application runtime. Such approach can be useful to speed-up verification as well as to implement hardware runtime monitors with respect to safety-critical applications. Existing tools and other related work are presented as well as two use cases which have been developed to benchmark the different approaches. The applicability of such flows in real-world applications is discussed, as well as possible traps and pitfalls when generating hardware out of hardware assertion languages. Finally, an outlook to future work based on the current results is given.
Starting Page	1
Ending Page	6
File Size	255101
Page Count	6
File Format	PDF
ISBN	9781479953264
DOI	10.1109/MESS.2014.7010247
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-05-08
Publisher Place	Austria
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	PSL Complexity theory Runtime Verification Assertion Synthesis Assertion-based Verification Test Automata Hardware Real-time systems System-on-chip Prototyping System Verilog Monitoring Clocks
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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