NDLI: Implementation of a driver circuit in 65nm CMOS technology for body-coupled communication

Content Provider	IEEE Xplore Digital Library
Author	Maruf, M.H. Korishe, A. Roy, S.
Copyright Year	2014
Description	Author affiliation: Dept. of ETE, Univ. of Liberal Arts Bangladesh, Dhaka, Bangladesh (Roy, S.) \|\| Dept. of Electr. Eng., Linkoping Univ., Linkoping, Sweden (Maruf, M.H.; Korishe, A.)
Abstract	This paper presents a newly cascaded voltage mode tri-state driver circuit for body-coupled communication (BCC) designed in 65 nm CMOS technology. Each stage of the driver circuit has been resized to meet the requirement of the BCC. It has a driving capability of 6 mA from 1.2 V supply with 10 MHz operating frequency. Different analysis has been performed to get the optimum results for the proposed circuit. The analysis shows cycle to cycle jitter to be less than one and power supply rejection ratio (PSRR) 65 dB, indicating the good emission of supply noise. In addition, the driver circuit does not require a filter to emit the noise because the body acts like a low pass filter.
Starting Page	1
Ending Page	4
File Size	440046
Page Count	4
File Format	PDF
ISBN	9781479948208
e-ISBN	9781479948192
DOI	10.1109/ICEEICT.2014.6919109
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-04-10
Publisher Place	Bangladesh
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decision support systems Electrical engineering BCC Conferences Corner analysis PSRR Noise analysis Communications technology Driver circuit
Content Type	Text
Resource Type	Article

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