NDLI: Development and analysis of C/A code generation of GPS receiver in FPGA and DSP

Content Provider	IEEE Xplore Digital Library
Author	Kumar, B.P. Paidimarry, C.S.
Copyright Year	2014
Description	Author affiliation: Dept. of ECE, Osmania Univ., Hyderabad, India (Kumar, B.P.; Paidimarry, C.S.)
Abstract	The Global Navigation Satellite System (GNSS) plays an important role in positioning and navigation applications. The Civilians are widely using GNSS in many applications like safety-life and positioning applications. The Global Positioning Service (GPS) augmentation is to achieve more reliable and accurate navigation solutions. The presently available traditional GNSS receivers are hardware based receivers which are not flexible and cannot be easily upgraded to acquire the signals from other GNSS systems. The aim of this work is to implement and develop a platform that allows developing a GPS software receiver using available signal processing techniques. This allows to test and implement a new algorithm which also permits to upgrade the receiver easily to new signal structures or even other navigation systems. In this paper we developed Coarse/Acquisition (C/A) code generator of GPS receiver and implemented in Virtes-5 FPGA and Blackfin 533 DSP boards by using Xilinx ISE 13.2 and Matlab 2010a respectively. The Agilent logic analyzer 1692-A is integrated with FPGA for accurate timing analysis.
Sponsorship	IEEE Chandigarh Subsect.
Starting Page	1
Ending Page	5
File Size	1616231
Page Count	5
File Format	PDF
e-ISBN	9781479922918
DOI	10.1109/RAECS.2014.6799658
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-03-06
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	DSP FPGA GNSS Receivers Software receiver Generators GPS Global Positioning System Logic Analayzer Satellites C/A code generation Digital signal processing Software Field programmable gate arrays
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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