NDLI: Implementation of HDLC controller design using Verilog HDL

Content Provider	IEEE Xplore Digital Library
Author	Nagpurwala, A.H. Sundaresan, C. Chaitanya, C.
Copyright Year	2013
Description	Author affiliation: SOIS, Manipal Univ., Manipal, India (Nagpurwala, A.H.; Sundaresan, C.; Chaitanya, C.)
Abstract	HDLC Protocol is used to send the data in the form of frames, a controller controls the flow of data in DATA LINK LAYER of OSI model. HDLC protocol is used to transmit frames in logic link layer of Data link Layer. HDLC frame consists of an 8 bit Flag bit as 01111110, followed by control bits, information bits, fcs bits (CRC), address bits and terminates with flag bit. It involves processing of data before transmission, termed as Zero Stuffing, which is a special feature of HDLC protocol. A FIFO is used to transmit the data in the order of First In First Out. When complete data is transmitted, FIFO generates empty signal and the transmission of fcs, control, information and address bits begins. In the receiver side, detection of flag bits marks the beginning of new frame and zero unstuffing of data is performed. The unstuffed data is stored in variable length memory. The architecture for HDLC protocol has been proposed in this paper. The proposed model is implemented and verified using Verilog HDL.
Starting Page	7
Ending Page	10
File Size	815506
Page Count	4
File Format	PDF
ISBN	9781479931774
e-ISBN	9781479931781
DOI	10.1109/ICEESE.2013.6895033
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-04
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Protocols Transmitters ISO standards Receivers Registers Peer-to-peer computing Hardware design languages
Content Type	Text
Resource Type	Article

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