NDLI: Vector-aware register allocation for GPU shader processors

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2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)

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Embedded system and application aware design of deregulated energy delivery systems

Optimizing mobile display brightness by leveraging human visual perception

QuadSeal: Quadruple algorithmic symmetrizing countermeasure against power based side-channel attacks

Approximate acceleration: A path through the era of dark silicon and big data

Does customizing inexactness help over simplistic precision (bit-width) reduction? A case study

Energy-interference-free system and toolchain support for energy-harvesting devices

Accuracy-aware optimization of approximate programs

Evaluating and exploiting impacts of dynamic power management schemes on system reliability

Exploiting cache conflicts to reduce radiation sensitivity of operating systems on embedded systems

Optimization of multi-channel BCH error decoding for common cases

PAC: Program Analysis for Approximation-aware Compilation

Approximation-aware Multi-Level Cells STT-RAM cache architecture

Quality-aware data allocation in approximate DRAM?

Vector-aware register allocation for GPU shader processors

A sparse matrix vector multiply accelerator for support vector machine

Saving memory movements through vector processing in the DRAM

Efficient SAT-based application mapping and scheduling on multiprocessor systems for throughput maximization

NUVA: Architectural support for runtime verification of parametric specifications over multicores

High performance and energy efficient wireless NoC-enabled multicore architectures for graph analytics

Timing characterization of OpenMP4 tasking model

Scheduling instruction effects for a statically pipelined processor

Reducing shift penalty in Domain Wall Memory through register locality

Self-powered wearable sensor platforms for wellness

Cognitive cameras: Assistive vision systems

Self-powered wearable sensor node: Challenges and opportunities

2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)

2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)

2011 Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES)

Vector-aware register allocation for GPU shader processors

Content Provider	IEEE Xplore Digital Library
Author	Yi-Ping You Szu-Chieh Chen
Copyright Year	2015
Description	Author affiliation: Dept. of Comput. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan (Yi-Ping You; Szu-Chieh Chen)
Abstract	Graphics processing units (GPUs) are now widely used in embedded systems for manipulating computer graphics and even for general-purpose computation. However, many embedded systems have to manage highly restricted hardware resources in order to achieve high performance or energy efficiency. The number of registers is one of the common limiting factors in an embedded GPU design. Programs that run with a low number of registers may suffer from high register pressure if register allocation is not properly designed, especially on a GPU in which a register is divided into four elements and each element can be accessed separately, because allocating a register for a vector-type variable that does not contain values in all elements wastes register spaces. In this paper we present a vector-aware register allocation framework to improve register utilization on shader architectures. The framework involves two major components: (1) element-based register allocation that allocates registers based on the element requirement of variables and (2) register packing that rearranges elements of registers in order to increase the number of contiguous free elements, thereby keeping more live variables in registers. Experimental results on a cycle-approximate simulator showed that the proposed framework decreased 92% of register spills in total and made 91.7% of 14 common shader programs spill-free. These results indicate an opportunity for energy management of the space that is used for storing spilled variables, with the framework improving the performance by a geometric mean of 8.3%, 16.3%, and 29.2% for general shader processors in which variables are spilled to memory with 5-, 10-, and 20-cycle access latencies, respectively. Furthermore, the reduction in the register requirement of programs enabled another 11 programs with high register pressure to be runnable on a lightweight GPU.
Starting Page	99
Ending Page	108
File Size	2218042
Page Count	10
File Format	PDF
ISBN	9781467383202
DOI	10.1109/CASES.2015.7324550
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-10-04
Publisher Place	Netherlands
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Program processors Shader processors Nickel Ice Register packing Register allocator Erbium
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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