NDLI: An effective 6-bit flash ADC using low power CMOS technology

Content Provider	IEEE Xplore Digital Library
Author	Reddy, M.S. Rahaman, S.T.
Copyright Year	2013
Description	Author affiliation: Dept. of Electron. & Commun. Eng., Vaagdevi Inst. of Technol. & Sci. affiliated to JNTU Anantapur - Proddatur, Anantapur, India (Reddy, M.S.) \|\| Dept. of Electron. & Commun. Eng., Sri Venkateswara Inst. of Sci. & Technol. affiliated to JNTU Anantapur - Kadapa, Anantapur, India (Rahaman, S.T.)
Abstract	In present day communication technology, Digital communication plays a tremendous role in effective power utilization of resources. In many aspects of Digital communication, both wired and wireless communication technologies are covered. To implement a digital communication system, Analog to Digital Conversion is must as the source of many systems is analog in nature. The effectiveness of Digital communication systems relay on speed of ADC. For this, there exist many types of ADCs such as Counter type ADC, Successive approximation type ADC, Flash Type ADC and Wilkinson type ADC. Among them Flash Type ADC has high ADC rate but with a drawback of high power consumptions. This drawback of high power consumption for Flash Type ADC is over come in our proposed method where a new 6-bit Flash Type ADC with less complexity and a conversion rate of 1-GS/s is implemented which results in low power consumption using low power CMOS technology. Here we use tools such as Micro Wind and Digital Schematic.
Starting Page	1
Ending Page	4
File Size	451817
Page Count	4
File Format	PDF
e-ISBN	9781467328180
DOI	10.1109/ICACT.2013.6710493
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-09-21
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multiplexing Micro Wind and Digital Schematic CMOS Power demand Latches Digital communication CMOS technology Complexity theory CMOS integrated circuits Key Words: ADC
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Reduced comparator low power flash ADC using 35nm CMOS

Power reduction techniques in a 6 bit 1 GSPS flash ADC

A 4.23-bit, 12.5 GS/s comparator for high speed flash ADC in BiCMOS technology

A 1-V 1-GS/s 6-bit low-power flash ADC in 90-nm CMOS with 15.75 mW power consumption

A 6-bit 800MS/s flash ADC in 0.35μm CMOS

Switched inverter comparator based 0.5 V low power 6 bit Flash ADC

Design of ultra low power novel 3-bit flash ADC in 45nm CMOS technology

2GSPS 6-bit ADC for UWB receivers

An ultra low power encoder for 5 bit flash ADC

An effective 6-bit flash ADC using low power CMOS technology

Similar Documents

Reduced comparator low power flash ADC using 35nm CMOS

Power reduction techniques in a 6 bit 1 GSPS flash ADC

A 4.23-bit, 12.5 GS/s comparator for high speed flash ADC in BiCMOS technology

A 1-V 1-GS/s 6-bit low-power flash ADC in 90-nm CMOS with 15.75 mW power consumption

A 6-bit 800MS/s flash ADC in 0.35μm CMOS

Switched inverter comparator based 0.5 V low power 6 bit Flash ADC

Design of ultra low power novel 3-bit flash ADC in 45nm CMOS technology

2GSPS 6-bit ADC for UWB receivers

An ultra low power encoder for 5 bit flash ADC

An effective 6-bit flash ADC using low power CMOS technology