NDLI: Design of FPGA-based rapid prototype spectral subtraction for hands-free speech applications

Content Provider	IEEE Xplore Digital Library
Author	Amornwongpeeti, S. Ono, N. Ekpanyapong, M.
Copyright Year	2014
Description	Author affiliation: Dept. of Microelectron. & Embedded Syst., Asian Inst. of Technol., Pathum Thani, Thailand (Ekpanyapong, M.) \|\| Principles of Inf. Res. Div., Nat. Inst. of Inf., Tokyo, Japan (Amornwongpeeti, S.; Ono, N.)
Abstract	In this paper, the design of a FPGA-based rapid prototype for Short-Time Fourier Transform (STFT) based spectral subtraction for hands-free speech applications using Xilinx System Generator (XSG) tools without traditional HDL hand coding is presented. Initially, the concept of a dual-channel short-time spectral subtraction algorithm for removing the wideband background noise in a speech signal is introduced. The studied algorithm is developed in the system-level modeling simulator using MATLAB Simulink environment. For the digital hardware design, simple hardware architectures for data framing and overlapping algorithms are proposed by utilizing the basic DSP blocksets of the XSG library, and replaced in the simulation model. Finally, a complete simulation model of the FPGA-based short-time spectral subtraction algorithm using XSG is presented. The comparative performance evaluation based on simulation results and the summary of resource utilization are confirmed the implementation feasibility of the real-time FPGA-based short-time spectral subtraction algorithm for hands-free speech applications.
Starting Page	1
Ending Page	6
File Size	464856
Page Count	6
File Format	PDF
ISBN	9786163618238
DOI	10.1109/APSIPA.2014.7041600
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-12-09
Publisher Place	Cambodia
Access Restriction	Subscribed
Rights Holder	Asia-Pacific Signal and Information Processing Ass
Subject Keyword	Decision support systems Algorithm design and analysis Fourier transforms Noise Speech Mathematical model Manganese
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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