NDLI: Design of time reduction for successive approximation register A/D converter

Content Provider	IEEE Xplore Digital Library
Author	Thin, Mon Mon Than, Myo Min
Copyright Year	2015
Description	Author affiliation: Department of Information Technology Engineering, Yangon Technological University (YTU), Yangon, Myanmar (Than, Myo Min) \|\| Department of Information Technology Engineering, Yangon Technological University (YTU) Yangon, Myanmar (Thin, Mon Mon)
Abstract	Acting as the gateway between the "real world" analog signal and digital signal, data converters have become a critical element of modern electronic devices. High-performance applications have put a particular emphasis on high-speed data conversion converters. A variety of converter architectures are being used to reach these higher speeds, each with special advantages. In modern life, the improvements of technologies and design methods have allowed to implement Successive Approximation Register (SAR) analog-to-digital converter (ADC) for higher performance. However, this converter has "N" time conversion steps required to digitize a sample for "N" bit due to the nature of successive approximation algorithm. To solve this situation, the new high performance architecture based on SAR ADC with charge redistribution DAC is created. In this paper, the proposed system modifies the SAR function to get high speed by reducing the number of bit cycles. Therefore, the proposed architecture can obtain better speed than the conventional architecture.
Starting Page	326
Ending Page	331
File Size	813460
Page Count	6
File Format	PDF
e-ISBN	9781467378635
DOI	10.1109/ICITEED.2015.7408966
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-10-29
Publisher Place	Thailand
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	ADC High-speed Digital-analog conversion SAR Conversion step Shift registers Information technology Analog-digital conversion Clocks Flip-flops
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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