NDLI: Architecture-aware graph repartitioning for data-intensive scientific computing

Content Provider	IEEE Xplore Digital Library
Author	Angen Zheng Labrinidis, A. Chrysanthis, P.K.
Copyright Year	2014
Description	Author affiliation: Dept. of Comput. Sci., Univ. of Pittsburgh, Pittsburgh, PA, USA (Angen Zheng; Labrinidis, A.; Chrysanthis, P.K.)
Abstract	Graph partitioning and repartitioning have been widely used by scientists to parallelize compute- and dataintensive simulations. However, existing graph (re)partitioning algorithms usually assume homogeneous communication costs among partitions, which contradicts the increasing heterogeneity in inter-core communication in modern parallel architectures and is further exacerbated by increasing dataset sizes (i.e., Big Data). To resolve this, we propose an architecture-aware graph repartitioner, called AragonLB. AragonLB considers the heterogeneity in both inter- and intra-node communication while rebalancing the load. Our experimental study with a turbulent combustion simulation dataset shows that AragonLB can result in up to 60% improvement against existing architecture-agnostic graph repartitioners (which assume uniform communication costs among partitions), and the improvement becomes more significant as the number of computation steps, the number of partitions, or the size of the interconnect increase.
Starting Page	78
Ending Page	85
File Size	938276
Page Count	8
File Format	PDF
ISBN	9781479956661
DOI	10.1109/BigData.2014.7004375
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-10-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Topology-Aware Frequency modulation Computational modeling Sockets Big data Partitioning algorithms Graph Repartitioning Scientific Computing Architecture-Aware Standards Load modeling Dynamic Load Balancing
Content Type	Text
Resource Type	Article

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