NDLI: One OpenCL to rule them all?

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One OpenCL to rule them all?

Content Provider	IEEE Xplore Digital Library
Author	Dolbeau, R. Bodin, F. de Verdiere, G.C.
Copyright Year	2013
Description	Author affiliation: CAPS entreprise, Rennes, France (Dolbeau, R.) \|\| IRISA, Rennes, France (Bodin, F.) \|\| CEA, DAM, Bruyères-le-Châtel, France (de Verdiere, G.C.)
Abstract	OpenCL is now available on a very large set of processors. This makes this language an attractive layer to address multiple targets with a single code base. The question on how sensitive to the underlying hardware is the OpenCL code in practice remains to be better understood. 1. This paper studies how realistic it is to use a unique OpenCL code for a set of hardware co-processors with different underlying micro-architectures. In this work, we target $Intel^{®}$ Xeon Phi™, $NVIDIA^{®}$ K20C and $AMD^{®}$ 7970™ GPU. All these accelerators provide at least support for OpenCL 1.1 and fit in the same high-end version of accelerator technology. To assess performance, we use OpenACC CAPS compiler to generate OpenCL code and use a moderately complex miniapplication, Hydro. This code uses 22 OpenCL kernels and was tailored to limit data transfers between the host and the accelerator device. To study how stable are the performance, we performed many experiments to determine the best OpenCL code for each hardware platform. This paper shows that, if well chosen, a single version of the code can be executed on multiple platforms without significant performance losses (less than 12%). This study confirms the need for auto-tuning technology to look for performance tradeoffs but also shows that deploying selftuning/adaptive code is not always necessary if the ultimate performance is not the goal.
Starting Page	1
Ending Page	6
File Size	274047
Page Count	6
File Format	PDF
ISBN	9781479910106
DOI	10.1109/MuCoCoS.2013.6633603
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-09-07
Publisher Place	UK
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Performance evaluation Graphics processing units Computer architecture Hardware Portability Code tuning Registers Performance Kernel Tuning GPGPU
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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