NDLI: Automatic validation of infinite real-time systems

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Automatic validation of infinite real-time systems

Content Provider	IEEE Xplore Digital Library
Author	Gothel, T. Glesner, S.
Copyright Year	2013
Description	Author affiliation: Tech. Univ. Berlin, Berlin, Germany (Gothel, T.; Glesner, S.)
Abstract	In safety-critical areas, complete and machine-assisted verification techniques for infinite real-time systems are required to ensure their correctness in all cases and to cope with their complexity. Previously, we presented a theorem prover-based comprehensive and compositional verification approach using the Timed CSP process calculus to model and verify possibly infinite real-time systems. However, it lacks support for employing automatic verification approaches to validate finite sub-processes of the overall system model. This mainly comes from insufficient automatic verification support for finite Timed CSP processes. In this paper, we present a real-time logic and a transformation of the Timed CSP process calculus to UPPAAL timed automata. We discuss their integration into our comprehensive verification approach as part of a prior validation phase. This is crucial because the effort for interactive verification in the theorem prover is thereby reduced considerably. By this, we provide a comprehensive machine-assisted verification approach without losing the benefits of automatic verification.
Starting Page	57
Ending Page	63
File Size	581049
Page Count	7
File Format	PDF
ISBN	9781467362924
DOI	10.1109/FormaliSE.2013.6612278
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-05-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semantics Automata Syntactics Real-time systems Calculus Synchronization Clocks
Content Type	Text
Resource Type	Article

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