Please wait, while we are loading the content...
| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Mishra, A. Pattanaik, M. Sharma, V. |
| Copyright Year | 2013 |
| Description | Author affiliation: ABV - Indian Inst. of Inf. Technol. & Manage., Gwalior, India (Mishra, A.; Pattanaik, M.; Sharma, V.) |
| Abstract | We investigate the deteriorating effect of source voltage on the performance of N-type vertical tunnel FETs. A non-zero source voltage may appear due to series connection of FETs. Theoretical analysis, backed with TCAD simulation, highlights the role of source voltage in undesired band bending and consequent change in various electrical parameters. We propose a double gate vertical tunnel FET structure as a solution to this problem. Such a structure nullifies any undesired bending in energy bands due to source voltage. Further, we utilize the proposed TFET to design hybrid CMOS-TFET based low standby power logic circuits; where the intrinsic properties of tunnel FET ensures the reduction of standby mode leakage current and supply voltage, while the modified tunnel FET enables the series connection of FETs. The proposed hybrid circuit utilizes minimum number of N-type tunnel FETs and hence minimizes the need for advanced and susceptible process steps associated with vertical tunnel FETs. Compared with conventional low standby power circuits, the hybrid combination shows four orders of reduction in sleep mode leakage current. |
| Sponsorship | IEEE Kerala Sect. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 273224 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781467351508 |
| e-ISBN | 9781467351492 |
| DOI | 10.1109/AICERA-ICMiCR.2013.6575992 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-06-04 |
| Publisher Place | India |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Double gate vertical tunnel FET (DGVTFET) Hybrid CMOS-TFET Field effect transistors Low standby power logic circuit Logic gates Tunneling Hybrid power systems Threshold voltage Topology Tunnel FET (TFET) |
| Content Type | Text |
| Resource Type | Article |
National Digital Library of India (NDLI) is a virtual repository of learning resources which is not just a repository with search/browse facilities but provides a host of services for the learner community. It is sponsored and mentored by Ministry of Education, Government of India, through its National Mission on Education through Information and Communication Technology (NMEICT). Filtered and federated searching is employed to facilitate focused searching so that learners can find the right resource with least effort and in minimum time. NDLI provides user group-specific services such as Examination Preparatory for School and College students and job aspirants. Services for Researchers and general learners are also provided. NDLI is designed to hold content of any language and provides interface support for 10 most widely used Indian languages. It is built to provide support for all academic levels including researchers and life-long learners, all disciplines, all popular forms of access devices and differently-abled learners. It is designed to enable people to learn and prepare from best practices from all over the world and to facilitate researchers to perform inter-linked exploration from multiple sources. It is developed, operated and maintained from Indian Institute of Technology Kharagpur.
Learn more about this project from here.
NDLI is a conglomeration of freely available or institutionally contributed or donated or publisher managed contents. Almost all these contents are hosted and accessed from respective sources. The responsibility for authenticity, relevance, completeness, accuracy, reliability and suitability of these contents rests with the respective organization and NDLI has no responsibility or liability for these. Every effort is made to keep the NDLI portal up and running smoothly unless there are some unavoidable technical issues.
Ministry of Education, through its National Mission on Education through Information and Communication Technology (NMEICT), has sponsored and funded the National Digital Library of India (NDLI) project.
| Sl. | Authority | Responsibilities | Communication Details |
|---|---|---|---|
| 1 | Ministry of Education (GoI), Department of Higher Education |
Sanctioning Authority | https://www.education.gov.in/ict-initiatives |
| 2 | Indian Institute of Technology Kharagpur | Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project | https://www.iitkgp.ac.in |
| 3 | National Digital Library of India Office, Indian Institute of Technology Kharagpur | The administrative and infrastructural headquarters of the project | Dr. B. Sutradhar bsutra@ndl.gov.in |
| 4 | Project PI / Joint PI | Principal Investigator and Joint Principal Investigators of the project |
Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon |
| 5 | Website/Portal (Helpdesk) | Queries regarding NDLI and its services | support@ndl.gov.in |
| 6 | Contents and Copyright Issues | Queries related to content curation and copyright issues | content@ndl.gov.in |
| 7 | National Digital Library of India Club (NDLI Club) | Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach | clubsupport@ndl.gov.in |
| 8 | Digital Preservation Centre (DPC) | Assistance with digitizing and archiving copyright-free printed books | dpc@ndl.gov.in |
| 9 | IDR Setup or Support | Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops | idr@ndl.gov.in |
|
Loading...
|