NDLI: Field-programmable gate array implementation of low-density parity-check codes decoder and hardware testbed

Content Provider	IEEE Xplore Digital Library
Author	Wetcharungsri, J. Buabthong, N. Jantarachote, S. Sangwongngam, P. Sripimanwat, K.
Copyright Year	2013
Description	Author affiliation: Nat. Electron. & Comput. Technol. Center (NECTEC), NSTDA, Pathumtani, Thailand (Sripimanwat, K.) \|\| Dept. of Electr. Eng., Thammasat Univ., Pathumthani, Thailand (Wetcharungsri, J.; Buabthong, N.; Jantarachote, S.; Sangwongngam, P.)
Abstract	The prototyping design of the channel coding in communication systems such as IEEE 802.16e (WiMAX) has become more sophisticated because of the increasing need for interoperability. Understanding its performance in the design and implementation of forward error correction codes in a real-time manner is necessary for rapid prototyping in research areas that are primarily based on emulation and stand-alone tests. This paper presents the design, implementation, experimental verification, and validation of the proposed LDPC decoder using a real-time FPGA based baseband test. The design of the LDPC decoder is described. In addition, a description of the hardware components that covers the important parts of the system from RF to channel decoding is included. The overall architecture of the baseband digital signal processing is simply illustrated, and details of the data acquisition module are provided. On the implementation and testing results, the throughput and latency at all the code rates specified in IEEE 802.16e are shown. Furthermore, the results for the architectural complexity and performance in terms of the bit error rates over the testbed show that the proposed flexible design for IEEE 802.16e exhibits potential under a practical environment.
Starting Page	104
Ending Page	107
File Size	438665
Page Count	4
File Format	PDF
ISBN	9781467363471
e-ISBN	9781467363495
DOI	10.1109/TENCONSpring.2013.6584426
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-04-17
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	IEEE 802.16 Standards Computer architecture Throughput Parity check codes Real-time systems Decoding Field programmable gate arrays
Content Type	Text
Resource Type	Article

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